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em78p341/2/3n 8-bit microprocessor with otp rom product specification d oc . v ersion 1.0 elan microelectronics corp. december 2006 www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents trademark acknowledgments : ibm is a registered trademark and ps/2 is a trademark of ibm. windows is a trademark of microsoft corporation. elan and elan logo are trademarks of elan mi croelectronics corporation. copyright ? 2005 by elan microelectronics corporation all rights reserved printed in taiwan the contents of this specification are subject to change without further notice. elan microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. elan microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. such information and material may change to conform to each confirmed order. in no event shall elan microelectronics be made responsi ble for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. elan microelectronics shall not be liable for direct, indirect, special in cidental, or consequential damages arising from the use of such information or material. the software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. elan microelectronics products are not intended for use in life support appliances, devices, or systems. use of elan microelectronics product in such applications is not supported and is prohibited. no part of this specification may be reprod uced or transmitted in any form or by any means without the expressed written permission of elan microelectronics. elan microelectronics corporation headquarters: no. 12, innovation road 1 hsinchu science park hsinchu, taiwan 30077 tel : +886 3 563-9977 fax : +886 3 563-9966 http : //www.emc.com.tw hong kong: elan (hk) microelectronics corporation, ltd. flat a, 19f., world tech centre 95 how ming street, kwun tong kowloon, hong kong tel : +852 2723-3376 fax : +852 2723-7780 elanhk@emc.com.hk usa: elan information technology group (u.s.a.) 1821 saratoga ave., suite 250 saratoga, ca 95070 u.s.a. tel : +1 408 366-8225 fax : +1 408 366-8220 europe: elan microelectronics corp. (europe) siewerdtstrasse 105 8050 zurich, switzerland tel : +41 43 299-4060 fax : +41 43 299-4079 http : //www.elan-europe.com shenzhen: elan microelectronics shenzhen, ltd. ssmec bldg., 3f, gaoxin s. ave. shenzhen hi-tech industrial park shenzhen, guandong, china tel : +86 755 2601-0565 fax : +86 755 2601-0500 shanghai: elan microelectronics shanghai, ltd. 23/bldg. #115 lane 572, bibo road zhangjiang hi-tech park shanghai, china tel : +86 21 5080-3866 fax : +86 21 5080-4600 www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents product specification (v1.0) 12.01.2006 ? iii contents 1 general d escripti on ................................................................................................ 3 2 features ................................................................................................................... 3 3 pin assignment ....................................................................................................... 4 4 functional bloc k diagra m ...................................................................................... 5 5 pin descr iption ........................................................................................................ 6 5.1 EM78P341N p/m............................................................................................... 6 5.2 em78p342n p/m............................................................................................... 7 5.3 em78p343n p/m/km......................................................................................... 8 6 function d escripti on .............................................................................................. 9 6.1 operational registers ....................................................................................... 9 6.1.1 r0 (indirect address register) .......................................................................... 9 6.1.2 r1 (time clock /counter) ................................................................................... 9 6.1.3 r2 (program counter) and stack ....................................................................... 9 6.1.3.1 data memory configuration................................................................11 6.1.4 r3 (status register) ......................................................................................... 12 6.1.5 r4 (ram select register) ................................................................................ 12 6.1.6 r5 ~ r6 (port 5 ~ port 6).................................................................................. 13 6.1.7 r7 (port 7) ........................................................................................................ 13 6.1.8 r8 (aisr: adc input select register) ............................................................. 14 6.1.9 r9 (adcon: adc control register) ................................................................ 15 6.1.10 ra (adoc: adc offset calibration register) .................................................. 17 6.1.11 rb (addata: converted value of adc) .......................................................... 17 6.1.12 rc (addata1h: converted value of adc) ..................................................... 17 6.1.13 rd (addata1l: converted value of adc) ...................................................... 18 6.1.14 re (interrupt status 2 & wake-up control register) ........................................ 18 6.1.15 rf (interrupt status 2 register)........................................................................ 19 6.1.16 r10 ~ r3f ........................................................................................................ 19 6.2 special purpose registers.............................................................................. 20 6.2.1 a (accumulator) ................................................................................................ 20 6.2.2 cont (control register) .................................................................................. 20 6.2.3 ioc50 ~ ioc70 (i/o port control register)...................................................... 21 6.2.4 ioc80 (comparator and tcca control register) ............................................ 21 6.2.5 ioc90 (tccb and tccc control register) ..................................................... 22 6.2.6 ioca0 (ir and tccc scale control register)................................................. 23 6.2.7 iocb0 (pull-down control register) ................................................................ 24 6.2.8 iocc0 (open-drain control register) ............................................................. 24 6.2.9 iocd0 (pull-high control register) .................................................................. 25 www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents iv ? product specification (v1.0) 12.01.2006 6.2.10 ioce0 (wdt control & interrupt mask registers 2) ........................................ 25 6.2.11 iocf0 (interrupt mask register) ...................................................................... 26 6.2.12 ioc51 (tcca counter) .................................................................................... 27 6.2.13 ioc61 (tccb counter) .................................................................................... 28 6.2.14 ioc71 (tccbh/msb counter)......................................................................... 28 6.2.15 ioc81 (tccc counter) .................................................................................... 28 6.2.16 ioc91 (low-time register).............................................................................. 29 6.2.17 ioca1 (high time register)............................................................................. 29 6.2.18 iocb1 high/low time scale control register)................................................ 29 6.2.19 iocc1 (tcc prescaler counter)...................................................................... 30 6.2.20 iocd1 (lvd control register) ......................................................................... 31 6.2.21 ioce1 (output sink select control register) .................................................. 32 6.2.21 iocf1 (pull-high control register)................................................................... 33 6.3 tcc/wdt and prescale r ................................................................................ 33 6.4 i/o ports ......................................................................................................... 35 6.4.1 usage of port 5 input change wake-up/interrupt function ............................. 37 6.5 reset and wake-up ........................................................................................ 37 6.5.1 reset and wake-up operation ......................................................................... 37 6.5.1.1 wake-up and interrupt modes operation summary.......................... 40 6.5.1.2 register initial values after reset ..................................................... 46 6.5.1.3 controller reset block diagram ........................................................ 51 6.5.2 the t and p status under status (r3) register ............................................... 51 6.6 interrupt .......................................................................................................... 52 6.7 analog-to-digital converter (adc) ................................................................. 55 6.7.1 adc control register (aisr/r8, adcon/r9, adoc/ra)............................... 55 6.7.1.1 r8 (aisr: adc input select register) .............................................. 55 6.7.1.2 r9 (adcon: ad control register).................................................... 56 6.7.1.3 ra (adoc: ad offset calibration register) ...................................... 57 6.7.3 adc sampling time ......................................................................................... 58 6.7.4 ad conversion time......................................................................................... 58 6.7.5 adc operation during sleep mode .................................................................. 59 6.7.6 programming proce ss/considerations ............................................................. 59 6.7.6.1 programming process ....................................................................... 59 6.7.6.2 sample demo programs ................................................................... 60 6.8 infrared remote control application/pwm waveform generation .................. 62 6.8.1 overview........................................................................................................... 62 6.8.2 function description ......................................................................................... 63 6.8.3 programming the related registers ............................................................... 65 6.9 timer/ counter ................................................................................................. 66 6.9.1 overview........................................................................................................... 66 6.9.2 function description ......................................................................................... 66 6.9.3 programming the related registers ................................................................ 68 www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents product specification (v1.0) 12.01.2006 ? v 6.10 comparator..................................................................................................... 68 6.10.1 external reference signal................................................................................ 69 6.10.2 comparator outputs ......................................................................................... 69 6.10.3 using a comparator as an operation amplifier ................................................ 70 6.10.4 comparator interrupt ........................................................................................ 70 6.10.5 wake-up from sleep mode ............................................................................... 70 6.11 osc illator ........................................................................................................ 71 6.11.1 oscillator modes ............................................................................................... 71 6.11.2 crystal oscillator/cer amic resonators (crystal) .............................................. 71 6.11.3 external rc oscillator mode ............................................................................ 73 6.11.4 internal rc oscillator mode ............................................................................. 74 6.12 power-on considerations................................................................................ 75 6.12.1 programmable wdt time-out period .............................................................. 75 6.12.2 external power-on reset circuit ...................................................................... 75 6.12.3 residual vo ltage protec tion ............................................................................. 76 6.13 code option ................................................................................................... 77 6.13.1 code option regi ster (word 0) ........................................................................ 77 6.13.2 code option regi ster (word 1) ........................................................................ 78 6.13.3 customer id register (word 2) ........................................................................ 79 6.14 low voltage detector...................................................................................... 80 6.14.1 low voltage reset............................................................................................ 80 6.14.2 low volta ge detector........................................................................................ 80 6.14.2.1 iocd1 (lvd control register) .......................................................... 80 6.14.2.2 re (interrupt status 2 & wake-up control register) ......................... 81 6.14.3 programming process ...................................................................................... 82 6.15 instruction set................................................................................................. 83 7 absolute maximum ratings.................................................................................. 85 8 dc electrical characteristics................................................................................ 85 8.1 ad converter characteristics ......................................................................... 86 8.2 comparator (op) characteristics.................................................................... 87 8.3 device characteristics .................................................................................... 88 9 ac electrical characteristic.................................................................................. 89 10 timing diagrams ................................................................................................... 90 www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents vi ? product specification (v1.0) 12.01.2006 appendix a. package type ........................................................................................................ 91 b packaging conf iguratio n ...................................................................................... 91 b.1 14-lead plastic dual in line (pdip) ? 300 mi l ................................................ 91 b.2 14-lead plastic small out line (sop) ? 150 mi l ............................................. 92 b.3 18-lead plastic dual in line (pdip) ? 300 mi l ................................................ 91 b.4 18-lead plastic small out line (sop) ? 300 mi l ............................................. 92 b.5 20-lead plastic shrink small outline (ssop) ? 209 mi l................................ 93 b.6 20-lead plastic dual-in-li ne (pdip) ? 300 mi l................................................ 94 b.7 20-lead plastic small out line (sopp) ? 300 mi l........................................... 95 c quality assurance and reliability ........................................................................ 96 c.1 address tr ap detect ....................................................................................... 96 specification revision history specification revision history doc. version revision description date 1.0 initial released version 2006/12/01 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 1 (this specification is subject to change without further notice) 1 general description the EM78P341N, em78p342n and em78p343n are 8-bit microprocessors designed and developed with low-power and high-speed cmos technology. the series have an on-chip 2k 13-bit electrical one time programmable read only memory (otp-rom). it provides a protection bit to prevent intrusion of user?s otp memory code. three code option bits are also available to meet user?s requirements. with enhanced otp-rom features, the EM78P341N, em78p342n and em78p343n provide a convenient way of developing and verifying user?s programs. moreover, this otp device offers the advantages of easy and effective program updates, using development and programming tools. user can avail of the elan writer to easily program his development code. 2 features ? cpu configuration ? 2k 13 bits on chip rom ? 80 8 bits on chip registers (sram) ? 8 level stacks for subroutine nesting ? 4 programmable level voltage detector (lvd) : 4.5v, 4.0v, 3.3v, 2.2v ? 4 programmable level voltage reset (lvr) : 4.0v, 3.5v, 2.7v, 1.8v (por) ? less than 1.5 ma at 5v/4mhz ? typically 15 a, at 3v/32khz ? typically 1 a, during sleep mode ? i/o port configuration ? three bidirectional i/o ports : p5, p6, p7 ? 18 i/o pins ? wake-up port : p5 ? 8 programmable pull-down i/o pins ? 16 programmable pull-high i/o pins ? 8 programmable open-drain i/o pins ? external interrupt : p60 ? operating voltage range: ? commercial version: operating voltage range 1.9v~5.5v ? industrial version: operating voltage range: 2.1v~5.5v ? operating temperature range : -40~85c ? commercial version: operating voltage range: 0c ~ 70c ? industrial version: operating voltage range: -40c ~ 85c ? operating frequency range: main clock ? crystal mode: dc ~ 20mhz/2clks @ 4v; dc ~16 mhz/2clks @ 3v dc ~ 4mhz/2clks @ 1.9v ? erc mode: dc ~ 4mhz/2clks @ 5v; dc ~ 4mhz/2clks @ 3v dc ~ 8mhz/2clks @ 3v; dc ~ 250ns inst. cycle @ 3v ? irc mode: oscillation mode : 4mhz , 16mhz, 1mhz, 455khz process deviation : typ3%, max5% temperature deviation : 10% (-40c~85c ) ? peripheral configuration ? easily implemented ir (or infrared remote control) ? 8-bit real time clock/counter (tcc) with selective signal sources, trigger edges, and overflow interrupt ? 8-bit real time clock/counter (tcca, tccc) and 16-bit real time clock/counter (tccb) with selective signal sources, trigger edges, and overflow interrupt ? 8-bit channels analog-to-digital converter with 12-bit resolution ? one pair of comparators or op ? seven available interrupts: ? tcc, tcca, tccb, tccc overflow interrupt ? input-port status changed interrupt (wake-up from sleep mode) ? external interrupt ? adc completion interrupt ? ir/pwm interrupt ? comparator status change interrupt ? low voltage detect (lvd) interrupt ? special features ? programmable free running watchdog timer (4.5ms:18ms) ? power saving sleep mode ? selectable oscillation mode ? power-on voltage detector available (1.7 v 0.1v) ? package type: ? 14-pin dip 300mil : EM78P341Np ? 14-pin sop 150mil : EM78P341Nm ? 18-pin dip 300mil : em78p342np ? 18-pin sop 300mil : em78p342nm ? 20-pin dip 300mil : em78p343np ? 20-pin sop 300mil : em78p343nm ? 20-pin ssop 209mil : em78p343nkm www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 2 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 3 pin assignment (1) 14-pin dip/sop p52/adc2 p53/adc3 p54/tcc/vref /reset vss p60//int p61/tcca p55/osci/adc6 p70/osco/adc5 vdd p67/ir out/adc4 EM78P341Np EM78P341Nm 1 2 3 4 5 6 7 14 13 12 11 10 9 8 p66/cin- p50/adc0 p51/adc1 fig. 3-1 14-pin EM78P341Np/nm (2) 18-pin dip/sop p52/adc2 p53/adc3 p54/tcc/vref /reset vss p60//int p61/tcca p62/tccb p63/tccc p55/osci/adc6 p70/osco/adc5 vdd p67/ir out/adc4 p65/cin+ em78p342np em78p342nm 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 p64/co 10 p66/cin- p50/adc0 p51/adc1 fig. 3-2 18-pin em78p342np/nm (3) 20-pin dip/sop/ssop 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p52/adc2 p53/adc3 p54/tcc/vref /reset vss p60//int p61/tcca p62/tccb p63/tccc p55/osci/adc6 p70/osco/adc5 vdd p67/ir out/adc4 p65/cin+ em78p343n p64/co p66/cin- p50/adc0 p51/adc1 p56 p57/adc7 fig. 3-3 20-pin em78p343np/nm/nkm www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 3 (this specification is subject to change without further notice) 4 functional block diagram rom r3 (status reg.) acc instruction decoder instruction register alu pc interrupt circuit 8-level stack (13 bit) interrupt control register oscillation generation ram mux ext. osc. r4 ext. rc int. rc start-up timer wdt tcca tccb tccc infrared remote control circuit tcc adc comparator (co) or op ain0~3 cin+ cin- co tcca tccc tccb ir out tcc ext int reset p6 p60 p67 p66 p65 p64 p63 p62 p61 p5 p50 p57 p56 p55 p54 p53 p52 p51 lvd lvr p71 p70 fig. 4-1 EM78P341N/342n/343n functional block diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 4 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 5 pin description 5.1 EM78P341Np/m symbol pin no. type function p50~p55 1~3, 12~14 i/o 6-bit general purpose input/output pins pull-high/pull-down wake up from sleep mode when the pin status changes default value at power-on reset p60, p61 66, 67 6~9 i/o 4-bit general purpose input/output pins open drain default value at power-on reset p70~p71 11, 4 i/o 2-bit general purpose input/output pins default value at power-on reset /int 6 i external interrupt pin triggered by a falling or a rising edge. defined by cont <7> adc0~adc6 1, 2, 9 11~14 i 7-bit analog-to-digital converter defined by adcon (r9)<1:0> vref 3 i external reference voltage for adc defined by adcon (r9) <7>. /reset 4 i general-purpose input only if it remains at logic low, the device will be reset wake-up from sleep mode when pin status changes voltage on /reset must not exceed vdd during normal mode tcc, tcca 3, 7 i external counter input tcc defined by cont<5> tcca defined by ioc80 <1> osci 12 i crystal type: crystal input terminal or external clock input pin rc type: rc oscillator input pin osco 11 o crystal type: output terminal for crystal oscillator or external clock input pin. rc type: clock output with a duration of one instruction cycle time. the prescaler is determined by the cont register. external clock signal input. ir out 13 o ir mode output pin. driving current = 10ma when the output voltage drops to vdd-0.5v at vdd = 5v sinking current = 15ma when the output voltage drops to gnd+0.5v at vdd = 5v vdd 10 ? power supply vss 5 ? ground www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 5 (this specification is subject to change without further notice) 5.2 em78p342np/m symbol pin no. type function p50~p55 1~3, 16~18 i/o 6-bit general purpose input/output pins pull-high/pull-down wake up from sleep mode when the pin status changes default value at power-on reset p60~67 6~13 i/o 8-bit general purpose input/output pins open drain default value at power-on reset p70~p71 15, 4 i/o 2-bit general purpose input/output pins default value at power-on reset /int 6 i external interrupt pin triggered by a falling or a rising edge. defined by cont <7> adc0~adc6 1, 2, 13 15~18 i 7-bit analog-to-digital converter defined by adcon (r9)<1:0> vref 3 i external reference voltage for adc defined by adcon (r9) <7>. cin- cin+ co 12 11 10 i i o ?-? : the input pin of vin- of the comparator ?+? : the input pin of vin+ of the comparator pin co is the comparator output defined by ioc80 <4 : 3> /reset 4 i general-purpose input only if it remains at logic low, the device will be reset wake-up from sleep mode when pin status changes voltage on /reset must not exceed vdd during normal mode tcc, tcca tccb, tccc 3, 7 8~9 i external counter input tcc defined by cont<5> tcca defined by ioc80 <1> tccb defined by ioc90 <5> tccc defined by ioc90 <1> osci 16 i crystal type: crystal input terminal or external clock input pin rc type: rc oscillator input pin osco 15 o crystal type: output terminal for crystal oscillator or external clock input pin. rc type: clock output with a duration of one instruction cycle time. the prescaler is determined by the cont register. external clock signal input. ir out 13 o ir mode output pin. capable of driving and sinking current = 20ma when the output voltage drops to 0.7vdd at rise to 0.3vdd at vdd = 5v vdd 14 ? power supply vss 5 ? ground www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 6 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 5.3 em78p343np/m/km symbol pin no. type function p50~p57 1~4, 17~20 i/o 8-bit general purpose input/output pins pull-high/pull-down wake up from sleep mode when the pin status changes default value at power-on reset p60~67 7~14 i/o 8-bit general purpose input/output pins open drain default value at power-on reset p70~p71 16, 5 i/o 2-bit general purpose input/output pins default value at power-on reset /int 7 i external interrupt pin triggered by a falling or a rising edge. defined by cont <7> adc0~adc7 2, 3, 14 16~20 i 8-bit analog-to-digital converter defined by adcon (r9) <2:0> vref 4 i external reference voltage for adc defined by adcon (r9) <7>. cin- cin+ co 13 12 11 i i o ?-? : the input pin of vin- of the comparator ?+? : the input pin of vin+ of the comparator pin co is the comparator output defined by ioc80 <4 : 3> /reset 5 i general-purpose input only if it remains at logic low, the device will be reset wake-up from sleep mode when pin status changes voltage on /reset must not exceed vdd during normal mode tcc, tcca tccb, tccc 4, 8 9~10 i external counter input tcc defined by cont<5> tcca defined by ioc80 <1> tccb defined by ioc90 <5> tccc defined by ioc90 <1> osci 17 i crystal type: crystal input terminal or external clock input pin rc type: rc oscillator input pin osco 16 o crystal type: output terminal for crystal oscillator or external clock input pin. rc type: clock output with a duration of one instruction cycle time. the prescaler is determined by the cont register. external clock signal input. ir out 14 o ir mode output pin. capable of driving and sinking current = 20ma when the output voltage drops to 0.7vdd at rise to 0.3vdd at vdd = 5v vdd 15 ? power supply vss 6 ? ground www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 7 (this specification is subject to change without further notice) 6 function description 6.1 operationa l registers 6.1.1 r0 (indirect address register) r0 is not a physically implemented register. its major function is to perform as an indirect address pointer. any instruction using r0 as a pointer, actually accesses the data pointed by the ram select register (r4). 6.1.2 r1 (time clock /counter) ? incremented by an external signal edge which is defined by the te bit (cont-4) through the tcc pin, or by the instruction cycle clock. ? writable and readable as any other registers ? the tcc prescaler counter (iocc1) is assigned to tcc ? the contents of the iocc1 register is cleared whenever ? ? a value is written to the tcc register. ? a value is written to the tcc prescaler bits (bits 3, 2, 1, 0 of the cont register) ? there is power-on reset, /reset, or wdt time out reset. 6.1.3 r2 (program counter) and stack a7 ~ a0 on-chip program memory 000h 7ffh 003h hardware interrupt vector user memory space reset vector a9 a8 a10 stack level 1 stack level 3 stack level 2 stack level 4 stack level 5 call 00 page0 0000~03ff 01 page1 0400~07ff r3 ret retl reti stack level 6 stack level 7 stack level 8 021h _ 3feh fig. 6-1 program counter organization ? r2 and hardware stacks are 11-bit wide. the structure is depicted in the table under section 6.1.3.1, data memory configuration (next page). ? generates 2k 13 bits on-chip rom addresses to the relative programming instruction codes. one program page is 1024 words long. ? the contents of r2 are all set to "0"s when a reset condition occurs. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 8 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) ? "jmp" instruction allows direct loading of the lower 10 program counter bits. thus, "jmp" allows pc to jump to any location within a page. ? "call" instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be located anywhere within a page. ? "ret" ("retl k", "reti") instruction loads the program counter with the contents of the top of stack. ? "add r2, a" allows a relative address to be added to the current pc, and the ninth and above bits of the pc will increase progressively. ? "mov r2, a" allows loading of an address from the "a" register to the lower 8 bits of the pc, and the ninth and tenth bits (a8 ~ a9) of the pc will remain unchanged. ? any instruction (except ?add r2,a?) that is written to r2 (e.g., "mov r2, a", "bc r2, 6", ????? ) will cause the ninth bit and the tenth bit (a8 ~ a9) of the pc to remain unchanged. ? in the case of EM78P341N/342n/343n, the most significant bit (a10) will be loaded with the content of ps0 in the status register (r3) upon execution of a "jmp", "call", or any other instructions set which write to r2. ? all instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions that are written to r2. note that these instructions need one or two instructions cycle as determined by code option register cyes bit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 9 (this specification is subject to change without further notice) 6.1.3.1 data memory configuration address r page registers iocx0 page registers 00 r0 (indirect addressing register) reserve 01 r1 (timer clock counter) 02 r2 (program counter) reserve 03 r3 (status register) reserve 04 r4 (ram select register) reserve 05 r5 (port 5) ioc50 (i/o port control register) 06 r6 (port 6) ioc60 (i/o port control register) 07 r7 (port 7) ioc70 (i/o port control register) 08 (adc input select register 09 0a 0b iocb0 (pull-down control register) 0c 0d 0e 0f iocf0 (interrupt mask register 1) 10 m 1f general registers 20 j 3f bank 0 bank 1 iocx1 page registers ioc80 (comparator and tcca control register) ioc90 (tccb and tccc control register) ioca0 (ir and tccc scale control register) iocc0 (open-drain control register) iocd0 (pull-high control register) ioce0 (wdt control register and interrupt mask register 2) ioc51 (tcca counter) ioc61 (tccb lsb counter) ioc71 (tccb hsb counter) ioc81 (tccc counter) ioc91 (low-time register) ioca1 (high-time register) iocb1 (high-time and low-time scale control register) reserve reserve reserve reserve reserve (lvd control register) (high output sink current) (pull-high control register) (adc control register) (adc offset calibration register) (converted value ad11~ad4 of adc) (converted value ad11~ad8 of adc) (converted value ad7~ad0 of adc) (interrupt status 2 and wake-up control register (interrupt status register 1) r9 ra rd re rf rb rc r8 iocc1 (tcc prescaler control) iocd1 ioce1 iocf1 reserve www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 10 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.1.4 r3 (status register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst iocs - t p z dc c bit 7 (rst): bit of reset type set to ?1? if wake-up from sleep on pin change, comparator status change, or ad conversion completed. set to ?0? if wake-up from other reset types. bit 6 (iocs): select the segment of io control register 0 = segment 0 (ioc50 ~ iocf0) selected 1 = segment 1 (ioc51 ~ iocc1) selected bit 5: not used (reserved) bit 4 (t): time-out bit. set to ?1? by the "slep" and "wdtc" commands or during power on , and reset to ?0? by wdt time-out (see section 6.5.2, the t and p status under status register for more details). bit 3 (p): power-down bit. set to ?1? during power-on or by a "wdtc" command and reset to ?0? by a "slep" command (see section 6.5.2, the t and p status under status register for more details). bit 2 (z): zero flag. set to "1" if the result of an arithmetic or logic operation is zero. bit 1 (dc): auxiliary carry flag bit 0 (c): carry flag 6.1.5 r4 (ram select register) bit 7: set to ?0? all the time bit 6: used to select bank 0 or bank 1 of register bits 5~0: used to select a register (address: 00~0f, 10~3f) in the indirect addressing mode see the table under section 6.1.3.1, data memory configuration . www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 11 (this specification is subject to change without further notice) 6.1.6 r5 ~ r6 (port 5 ~ port 6) r5 & r6 are i/o registers the upper two bits of r5 are fixed to ?0? (if em78p342n is selected). only the lower six bits of r5 are available (this applies to em78p342n only since em78p343n can use all the bits) 6.1.7 r7 (port 7) bit 7 6 5 4 3 2 1 0 em78p342n/343n ?0? ?0? ?0? ?0? ?0? ?0? i/o i/o ice342n c3 c2 c1 c0 rcm1 rcm0 i/o i/o note ? r7 is an i/o register ? for em78p342n/343n, only the lower 2 bit of r7 is available. bit 7 ~ bit 2: [with em78p342n/343n]: unimplemented, read as ?0?. [with simulator (c3~c0, rcm1, & rcm0)]: irc calibration bits in irc oscillator mode. in irc oscillator mode of ice342n simulator, these are the irc mode selection bits and irc calibration bits. bit 7 ~ bit 4 (c3 ~ c0): calibrator of internal rc mode c3 c2 c1 c0 frequency (mhz) 0 0 0 0 (1-36%) x f 0 0 0 1 (1-31.5%) x f 0 0 1 0 (1-27%) x f 0 0 1 1 (1-22.5%) x f 0 1 0 0 (1-18%) x f 0 1 0 1 (1-13.5%) x f 0 1 1 0 (1-9%) x f 0 1 1 1 (1-4.5%) x f 1 1 1 1 f (default) 1 1 1 0 (1+4.5%) x f 1 1 0 1 (1+9%) x f 1 1 0 0 (1+135%) x f 1 0 1 1 (1+18%) x f 1 0 1 0 (1+22.5%) x f 1 0 0 1 (1+27%) x f 1 0 0 0 (1+31.5%) x f note: 1. frequency values shown are theoretical and taken from an instance of a high frequency mode. hence, they are shown for reference only. definite values depend on the actual process. 2. similar way of calculation is also applicable for low frequency mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 12 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) bit 3 & bit 2 (rcm1, rcm0): irc mode selection bits rcm 1 rcm 0 frequency (mhz) 1 1 4 (default) 1 0 16 0 1 1 0 0 455khz 6.1.8 r8 (aisr: adc input select register) the aisr register defines the i/o port as analog inputs or as digital i/o, individually. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 bit 7 (ade7): ad converter enable bit of p57 pin 0 = disable adc7, p57 functions as i/o pin 1 = enable adc7 to function as analog input pin bit 6 (ade6): ad converter enable bit of p55 pin 0 = disable adc6, p55 functions as i/o pin 1 = enable adc6 to function as analog input pin bit 5 (ade5): ad converter enable bit of p70 pin 0 = disable adc5, p70 functions as i/o pin 1 = enable adc5 to function as analog input pin bit 4 (ade4): ad converter enable bit of p67 pin 0 = disable adc4, p67 functions as i/o pin 1 = enable adc4 to function as analog input pin bit 3 (ade3): ad converter enable bit of p53 pin 0 = disable adc3, p53 functions as i/o pin 1 = enable adc3 to function as analog input pin bit 2 (ade2): ad converter enable bit of p52 pin 0 = disable adc2, p52 functions as i/o pin 1 = enable adc2 to function as analog input pin bit 1 (ade1): ad converter enable bit of p51 pin 0 = disable adc1, p51 functions as i/o pin 1 = enable adc1 to function as analog input pin bit 0 (ade0): ad converter enable bit of p50 pin. 0 = disable adc0, p50 function as i/o pin 1 = enable adc0 to function as analog input pin www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 13 (this specification is subject to change without further notice) note the p55/osci/adc6 pin cannot be applied to osci and adc6 at the same time. if p55/osci/adc6 functions as osci oscillator input pin, then ade6 bit for r8 must be ?0? and adis2~0 do not select ? 110?. the p55/osci/adc6 pin priority is as follows: the p70/osco/adc5 pin cannot be applied to osco and adc5 at the same time. if p70/osco/adc5 acts as osco oscillator input pin, then ade5 bit for r8 must be ?0? and adis2~0 do not select ?101?. the p70/osco/adc5 pin priority is as follows: the p66/ir out/adc4 pin cannot be applied to ir out and adc4 at the same time. if p67/ir out/adc4 functions as adc4 analog input pin, then iroute bit for ioca0 must be ?0?.. if p67/ir out/adc4 functions as ir out analog input pin, then ade4 bit for r8 must be ?0? and adis2~0 do not select ?100?. the p67/ir out/adc4 pin priority is as follows: 6.1.9 r9 (adcon: adc control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrefs ckr1 ckr0 adrun adpd adis2 adis1 adis0 bit 7 (vrefs): the input source of the vref of the adc 0 = the vref of the adc is connected to vdd (default value), and the vref/tcc/p54 pin carries out the function of p54 1 = the vref of the adc is connected to vref/tcc/p54 p55/osci/adc6 pin priority high medium low osci adc6 p55 p67/ir out/adc4 pin priority high medium low adc7 ir out p67 p70/osco/adc5 pin priority high medium low osco adc5 p70 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 14 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) note ? the p54/tcc/vref pin cannot be applied to tcc and vref at the same time. if p53/tcc/vref functions as vref analog input pin, then cont bit 5 ?ts? must be ?0.? ? the vref/tcc/p54 pin priority is as follows: bit 6 & bit 5 (ckr1 & ckr0): the prescaler of adc oscillator clock rate 00 = 1 : 16 (default value) 01 = 1 : 4 10 = 1 : 64 11 = 1 : 8 cpus ckr1:ckr0 operation mode max. operation frequency 1 00 fosc/16 4mhz 1 01 fosc/4 1mhz 1 10 fosc/64 16mhz 1 11 fosc/8 2mhz 0 xx internal rc - bit 4 (adrun): adc starts to run. 1 = an ad conversion is started. this bit can be set by software 0 = reset upon completion of the conversion. this bit cannot be reset through software bit 3 (adpd): adc power-down mode 1 = adc is operating 0 = switch off the resistor reference to save power even while the cpu is operating bit 2 ~ bit 0 (adis2 ~adis0): analog input select 000 = adin0/p50 001 = adin1/p51 010 = adin2/p52 011 = adin3/p53 100 = adin0/p67 101 = adin1/p70 110 = adin2/p55 111 = adin3/p57 these bits can only be changed when the adif bit (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) and the adrun bit are both low. p53/tcc/vref pin priority high medium low vref tcc p54 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 15 (this specification is subject to change without further notice) 6.1.10 ra (adoc: adc offset calibration register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cali sign vof[2] vof[ 1] vof[0] ?0? ?0? ?0? bit 7 (cali): calibration enable bit for adc offset 0 = calibration disable 1 = calibration enable bit 6 (sign): polarity bit of offset voltage 0 = negative voltage 1 = positive voltage bit 5 ~ bit 3 (vof[2] ~ vof[0]): offset voltage bits vof[2] vof[1] vof[0] em78p342n/343n ice342n 0 0 0 0lsb 0lsb 0 0 1 2lsb 2lsb 0 1 0 4lsb 4lsb 0 1 1 6lsb 6lsb 1 0 0 8lsb 8lsb 1 0 1 10lsb 10lsb 1 1 0 12lsb 12lsb 1 1 1 14lsb 14lsb bit 2 ~ bit 0: unimplemented, read as ?0? 6.1.11 rb (addata: converted value of adc) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 when the ad conversion is completed, the result is loaded into the addata. the adrun bit is cleared, and the adif (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) is set. rb is read only. 6.1.12 rc (addata1h: converted value of adc) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 1 0 ?0? ?0? ?0? ?0? ad11 ad10 ad9 ad8 when the ad conversion is completed, the result is loaded into the addata1h. the adrun bit is cleared, and the adif (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) is set. rc is read only www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 16 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.1.13 rd (addata1l: converted value of adc) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 when the ad conversion is completed, the result is loaded into the addata1l. the adrun bit is cleared, and the adif (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) is set. rd is read only 6.1.14 re (interrupt status 2 & wake-up control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 /lvd lvdif adif cmpif adwe cmpwe icwe lvdwe note re <5,4> can be cleared by instruction but cannot be set. ioce0 is the interrupt mask register. reading re will result to "logic and" of re and ioce0. bit 7 (/lvd): low voltage detector state. this is a read only bit. when the vdd pin voltage is lower than lvd voltage interrupt level (selected by lvd1 and lvd0), this bit will be cleared. 0 = low voltage is detected 1 = low voltage is not detected or lvd function is disabled bit 6 (lvdif): low voltage detector interrupt flag lvdif is reset to ?0? by software. bit 5 (adif): interrupt flag for analog to digital conversion. set when ad conversion is completed. reset by software. 0 = no interrupt occurs 1 = interrupt request bit 4 (cmpif): comparator interrupt flag. set when a change occurs in the comparator output. reset by software. 0 = no interrupt occurs 1 = interrupt request bit 3 (adwe): adc wake-up enable bit 0 = disable adc wake-up 1 = enable adc wake-up when ad conversion enters sleep mode, this bit must be set to ?enable?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 17 (this specification is subject to change without further notice) bit 2 (cmpwe): comparator wake-up enable bit 0 = disable comparator wake-up 1 = enable comparator wake-up when comparator enters sleep mode, this bit must be set to ?enable?. bit 1 (icwe): port 5 input change to wake-up status enable bit 0 = disable port 5 input change to wake-up status 1 = enable port 5 input change to wake-up status when port 5 change enters sleep mode, this bit must be set to ?enable?. bit 0 (lvdwe): low voltage detect wake-up enable bit 0 = disable low voltage detect wake-up 1 = enable low voltage detect wake-up when the low voltage detect is used to enter an interrupt vector or to wake-up the ic from sleep with low voltage detect running, the lvdwe bit must be set to ?enable?. 6.1.15 rf (interrupt status 2 register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lpwtif hpwtif tcccif tccbif tccaif exif icif tcif note ?1? means there is interrupt request; ?0? means no interrupt occurs rf can be cleared by instruction but cannot be set. iocf0 is the relative interrupt mask register. reading rf will result to "logic and" of rf and iocf0. bit 7 (lpwtif): internal low-pulse width timer underflow interrupt flag for ir/pwm function. reset by software. bit 6 (hpwtif): internal high-pulse width timer underflow interrupt flag for ir/pwm function. reset by software. bit 5 (tcccif): tccc overflow interrupt flag. set when tccc overflows. reset by software. bit 4 (tccbif): tccb overflow interrupt flag. set when tccc overflows. reset by software. bit 3 (tccaif): tcca overflow interrupt flag. set when tccc overflows. reset by software. bit 2 (exif): external interrupt flag. set by falling edge on /int pin. reset by software. bit 1 (icif): port 5 input status change interrupt flag. set when port 5 input changes. reset by software. bit 0 (tcif): tcc overflow interrupt flag. set when tcc overflows. reset by software. 6.1.16 r10 ~ r3f all of these are 8-bit general-purpose registers. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 18 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.2 special pur pose registers 6.2.1 a (accumulator) internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the accumulator. the accumulator is not an addressable register. 6.2.2 cont (control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inte int ts te pste pst2 pst1 pst0 note the cont register is both readable and writable. bit 6 is read only. bit 7 (inte): int signal edge 0 = interrupt occurs at a rising edge on the int pin 1 = interrupt occurs at a falling edge on the int pin bit 6 (int): interrupt enable flag 0 = masked by disi or hardware interrupt 1 = enabled by the eni/reti instructions this bit is readable only. bit 5 (ts): tcc signal source 0 = internal instruction cycle clock. p54 is bi-directional i/o pin. 1 = transition on the tcc pin bit 4 (te): tcc signal edge 0 = increment if the transition from low to high takes place on the tcc pin 1 = increment if the transition from high to low takes place on the tcc pin. bit 3 (pste): prescaler enable bit for tcc 0 = prescaler disable bit. tcc rate is 1:1. 1 = prescaler enable bit. tcc rate is set as bit 2 ~ bit 0. bit 2 ~ bit 0 (pst2 ~ pst0): tcc prescaler bits pst2 pst1 pst0 tcc rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 note: tcc time-out period [1/fosc x prescaler x 256 (tcc cnt) x 1 (clk=2)] tcc time-out period [1/fosc x prescaler x 256 (tcc cnt) x 2 (clk=4)] www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 19 (this specification is subject to change without further notice) 6.2.3 ioc50 ~ ioc70 (i/o port control register) ? " 1 " sets the relative i/o pin into high impedance, while " 0 " defines the relative i/o pin as output. ? only the lower six bits of ioc50 can be defined (this applies to EM78P341N/342n only since all bits of em78p343n can be used). ? only bit 0, bit 1, bit 6, bit 7 of ioc60 can be defined (this applies to EM78P341N only since all bits of em78p343n can be used) ? only the lower two bits of ioc70 can be defined, the others bits are not available. ? ioc50 , ioc60 , and ioc70 registers are all readable and writable 6.2.4 ioc80 (comparator and tcca control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? cmpout cos1 cos0 tccaen tccats tccate note bits 4 ~ 0 of the ioc80 register are both readable and writable EM78P341N cannot use the op/comparator function bit 5 of the ioc80 register is readable only. bit 7 & bit 6: not used bit 5 (cmpout): result of the comparator output. this bit is readable only. bit 4 & bit 3 (cos1 & cos0): comparator/op select bits cos1 cos0 function description 0 0 comparator and op are not used. p64, p65, and p66 function as normal i/o pin 0 1 used as comparator and p64 functions as normal i/o pin 1 0 used as comparator and p64 functions as comparator output pin (co) 1 1 used as op and p64 functions as op output pin (co) bit 2 (tccaen): tcca enable bit 0 = disable tcca 1 = enable tcca as a counter bit 1 (tccats): tcca signal source 0 =: internal instruction cycle clock. p61 is a bidirectional i/o pin. 1 = transit through the tcca pin bit 0 (tccate): tcca signal edge 0 = increment if transition from low to high takes place on the tcca pin 1 = increment if transition from high to low takes place on the tcca pin www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 20 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.2.5 ioc90 (tccb and tccc control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tccbhe tccben tccbts tccbte ? tcccen tcccts tcccte note the EM78P341N cannot define bit 5, bit 4, bit 1, and bit 0 of the ioc90. bit 7 (tccbhe): control bit is used to enable the most significant byte of the counter 1 = enable the most significant byte of tccbh tccb is a 16-bit counter. 0 = disable the most significant byte of tccbh (default value) tccb is an 8-bit counter. bit 6 (tccben): tccb enable bit 0 = disable tccb 1 = enable tccb as a counter bit 5 (tccbts) tccb signal source 0 = internal instruction cycle clock. p62 is a bi-directional i/o pin. 1 = transit through the tccb/p62 pin bit 4 (tccbte): tccb signal edge 0 = increment if the transition from low to high takes place on the tccb pin 1 = increment if the transition from high to low takes place on the tccb pin bit 3: not used. bit 2 (tcccen): tccc enable bit 0 = disable tccc 1 = enable tccc as a counter bit 1 (tcccts) tccc signal source 0 = internal instruction cycle clock. p63 is a bidirectional i/o pin. 1 = transit through the tccc/p63 pin bit 0 (tcccte): tccc signal edge 0 = increment if the transition from low to high takes place on the tccc pin 1 = increment if the transition from high to low takes place on the tccc pin www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 21 (this specification is subject to change without further notice) 6.2.6 ioca0 (ir and tccc scale control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcccse tcccs2 tcccs1 tcccs0 ire hf lgp iroute bit 7 (tcccse): scale enable bit for tccc an 8-bit counter is provided as scale for tccc and ir-mode. when in ir-mode, tccc counter scale uses the low-time segments of the pulse generated by fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). 0 = scale disable bit, tccc rate is 1 : 1 1 = scale enable bit, tccc rate is set as bit 6 ~ bit 4 bit 6 ~ bit 4 (tcccs2 ~ tcccs0): tccc scale bits the tcccs2 ~ tcccs0 bits of the ioca0 register are used to determine the scale ratio of tccc as shown below : tcccs2 tcccs1 tcccs0 tccc rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3 (ire): infrared remote enable bit 0 = disable ire, i.e., disable h/w modulator function. the irout pin is fixed at a high level and the tccc is an up counter. 1 = enable ire, i.e., enable h/w modulator function. pin 67 is defined as irout. if hp=1, the tccc counter scale uses the low-time segments of the pulse generated by the fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). when hp=0, the tccc is an up counter. bit 2 (hf): high frequency bit 0 = pwm application. irout waveform is achieved base on the high-pulse width timer and low-pulse width timer which determine the high time width and low time width respectively. 1 = ir application mode. the low-time segments of the pulse generated by the fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ) bit 1 (lgp): long pulse. 0 = the high-time and low-time registers are valid 1 = the high-time register is ignored. a single pulse is generated. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 22 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) bit 0 (iroute): control bit used to define the p67 (irout) pin function 0 = p67 defined as bi-directional i/o pin 1 = p67 defined as irout. under this condition, the i/o control bit of p67 (bit 7 of ioc60) must be set to ?0? 6.2.7 iocb0 (pull-down control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 /pd57 /pd56 /pd55 /pd54 /pd53 /pd52 /pd51 /pd50 note iocb0 register is both readable and writable bit 7 (/pd57): control bit used to enable the pull-down function of the p57 pin (applicable to em78p343n only) 0 = enable internal pull-down 1 = disable internal pull-down bit 6 (/pd56): control bit is used to enable the pull-down function of the p56 pin (applicable to em78p343n only) bit 5 (/pd55): control bit used to enable the pull-down function of the p55 pin bit 4 (/pd54): control bit used to enable the pull-down function of the p54 pin bit 3 (/pd53): control bit used to enable the pull-down function of the p53 pin bit 2 (/pd52): control bit used to enable the pull-down function of the p52 pin bit 1 (/pd51): control bit used to enable the pull-down function of the p51 pin bit 0 (/pd50): control bit used to enable the pull-down function of the p50 pin. 6.2.8 iocc0 (open-drain control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 /od67 /od66 /od65 /od64 /od63 /od62 /od61 /od60 note the iocc0 register is both readable and writable. bit 7 (/od67): control bit is used to enable the open-drain output of the p67 pin 0 = enable open-drain output 1 = disable open-drain output bit 6 (/od66): control bit used to enable the open-drain output of the p66 pin bit 5 (/od65): control bit used to enable the open-drain output of the p65 pin (not applicable to EM78P341N) www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 23 (this specification is subject to change without further notice) bit 4 (/od64): control bit used to enable the open-drain of the p64 pin (not applicable to EM78P341N) bit 3 (/od63): control bit used to enable the open-drain of the p63 pin (not applicable to EM78P341N) bit 2 (/od62): control bit used to enable the open-drain of the p62 pin (not applicable to EM78P341N) bit 1 (/od61): control bit used to enable the open-drain of the p61 pin bit 0 (/od60): control bit used to enable the open-drain of the p60 pin 6.2.9 iocd0 (pull-high control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 /ph57 /ph56 /ph55 /ph54 /ph53 /ph52 /ph51 /ph50 note the iocd0 register is both readable and writable. bit 7 (/ph57): control bit is used to enable the pull-high of the p57 pin (applicable to em78p343n only). 0 = enable internal pull-high 1 = disable internal pull-high bit 6 (/ph56): control bit used to enable the pull-high function of the p56 pin (applicable to em78p343n only). bit 5 (/ph55): control bit used to enable the pull-high function of the p55 pin. bit 4 (/ph54): control bit used to enable the pull-high function of the p54 pin. bit 3 (/ph53): control bit used to enable the pull-high function of the p53 pin. bit 2 (/ph52): control bit used to enable the pull-high function of the p52 pin. bit 1 (/ph51): control bit used to enable the pull-high function of the p51 pin. bit 0 (/ph50): control bit used to enable the pull-high function of the p50 pin. 6.2.10 ioce0 (wdt control & interrupt mask registers 2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdte eis adie cmpie pswe psw2 psw1 psw0 bit 7 (wdte): control bit used to enable watchdog timer 0 = disable wdt 1 = enable wdt wdte is both readable and writable. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 24 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) bit 6 (eis): control bit used to define the function of the p60 (/int) pin 0 = p60, bidirectional i/o pin 1 = /int, external interrupt pin. in this case, the i/o control bit of p60 (bit 0 of ioc60) must be set to "1". note when eis is "0", the path of /int is masked. when eis is "1", the status of /int pin can also be read by way of reading port 6 (r6). refer to fig. 6-3 (i/o port and i/o control register circuit for p60 (/int)) under section 6.4 (i/o ports). eis is both readable and writable. bit 5 (adie): adif interrupt enable bit 0 = disable adif interrupt 1 = enable adif interrupt bit 4 (cmpie ) : cmpif interrupt enable bit. 0 = disable cmpif interrupt 1 = enable cmpif interrupt bit 3 (pswe): prescaler enable bit for wdt 0 = prescaler disable bit, wdt rate is 1:1 1 = prescaler enable bit, wdt rate is set as bit 2 ~ bit 0 bit 2 ~ bit 0 (psw2 ~ psw0): wdt prescaler bits psw2 psw1 psw0 wdt rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.2.11 iocf0 (interrupt mask register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lpwtie hpwtie tcccie tccbie tccaie exie icie tcie www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 25 (this specification is subject to change without further notice) note the iocf0 register is both readable and writable. individual interrupt is enabled by setting its associated control bit in the iocf0 and in ioce0 bit 4 & 5 to "1". global interrupt is enabled by the eni instruction and is disabled by the disi instruction. refer to fig. 6-7 (interrupt input circuit) under section 6.6 (interrupt). bit 7 (lpwtie): lpwtif interrupt enable bit 0 = disable lpwtif interrupt 1 = enable lpwtif interrupt bit 6 (hpwtie): hpwtif interrupt enable bit 0 = disable hpwtif interrupt 1 = enable hpwtif interrupt bit 5 (tcccie): tcccif interrupt enable bit 0 = disable tcccif interrupt 1 = enable tcccif interrupt bit 4 (tccbie): tccbif interrupt enable bit 0 = disable tccbif interrupt 1 = enable tccbif interrupt bit 3 (tccaie): tccaif interrupt enable bit 0 = disable tccaif interrupt 1 = enable tccaif interrupt bit 2 (exie): exif interrupt enable bit 0 = disable exif interrupt 1 = enable exif interrupt bit 1 (icie): icif interrupt enable bit 0 = disable icif interrupt 1 = enable icif interrupt bit 0 (tcie): tcif interrupt enable bit. 0 = disable tcif interrupt 1 = enable tcif interrupt 6.2.12 ioc51 (tcca counter) ioc51 (tcca) is an 8-bit clock counter. it can be read, written, and cleared on any reset condition and is an up counter. note tcca timeout period [1/fosc x (256-tcca cnt) x 1(clk=2)] tcca timeout period [1/fosc x (256-tcca cnt) x 2 (clk=4)] www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 26 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.2.13 ioc61 (tccb counter) ioc61 (tccb) is an 8-bit clock counter for the least significant byte of tccbx (tccb) . it can be read, written, and cleared on any reset condition and it is an up counter. 6.2.14 ioc71 (tccbh/msb counter) ioc71 (tccbh/msb) is an 8-bit clock counter for the most significant byte of tccbx (tccbh) . it can be read, written, and cleared on any reset condition. when tccbhe (ioc90) is ? 0 ,? then tccbh is disabled. when tccbhe is? 1 ,? then tccb is a 16-bit counter. note when tccbh is disabled: tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 1 (clk=2)] tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 2 (clk=4)] when tccbh is enabled: tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 1 (clk=2)} tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 2 (clk=4)} 6.2.15 ioc81 (tccc counter) ioc81 (tccc) is an 8-bit clock counter that can be extended to 16-bit counter. it can be read, written, and cleared on any reset condition. if hf (bit 2 of ioca0) = 1 and ire (bit 3 of ioca0) = 1, tccc counter scale uses the low-time segments of the pulse generated by the fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). then tccc value will be tccc predicted value. when hp = 0 or ire = 0, the tccc is an up counter. note in tccc up counter mode: tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 1 (clk=2)] tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 2 (clk=4)] when hp = 1 and ire = 1, tccc counter scale uses the low-time segments of the pulse generated by the fcarrier frequency modulation. note in ir mode: fcarrier = ft/ 2 { [1+decimal tccc counter value (ioc81)] * tccc scale (ioca0) } ft is system clock : ft = fosc/1 (clk=2) ft = fosc/2 (clk=4) www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 27 (this specification is subject to change without further notice) 6.2.16 ioc91 (low-time register) the 8-bit low-time register controls the active or low segment of the pulse. the decimal value of its contents determines the number of oscillator cycles and verifies that the ir out pin is active. the active period of ir out can be calculated as follows : note low time width = { [1+decimal low-time value (ioc91)] * low time scale (iocb1) } / ft ft is system clock : ft = fosc/1 (clk=2) ft = fosc/2 (clk=4) when an interrupt is generated by the low time down counter underflow (if enabled), the next instruction will be fetched from address 015h (low time). 6.2.17 ioca1 (high time register) the 8-bit high-time register controls the inactive or high period of the pulse. the decimal value of its contents determines the number of oscillator cycles and verifies that the ir out pin is inactive. the inactive period of ir out can be calculated as follows : note high time width = {[1+decimal high-time value (ioca1)] * high time scale (iocb1) } / ft ft is system clock : ft=fosc/1(clk=2) ft=fosc/2(clk=4) when an interrupt is generated by the high time down counter underflow (when enabled), the next instruction will be fetched from address 012h (high time). 6.2.18 iocb1 high/low time scale control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 htse hts2 hts1 hts0 ltse lts2 lts1 lts0 bit 7 (htse): high-time scale enable bit 0 = scale disable bit, high-time rate is 1 : 1 1 = scale enable bit, high-time rate is set as bit 6~bit 4. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 28 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) bit 6 ~ bit 4 (hts2 ~ hts0): high-time scale bits : hts2 hts1 hts0 high-time rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3 (ltse): low-time scale enable bit. 0 = scale disable bit, low-time rate is 1:1 1 = scale enable bit, low-time rate is set as bit 2~bit 0. bit 2 ~ bit 0 (lts2 ~ lts0): low-time scale bits : lts2 lts1 lts0 low-time rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.2.19 iocc1 (tcc prescaler counter) tcc prescaler counter can be read and written to : pst2 pst1 pst0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcc rate 0 0 0 - - - - - - - v 1:2 0 0 1 - - - - - - v v 1:4 0 1 0 - - - - - v v v 1:8 0 1 1 - - - - v v v v 1:16 1 0 0 - - - v v v v v 1:32 1 0 1 - - v v v v v v 1:64 1 1 0 - v v v v v v v 1:128 1 1 1 v v v v v v v v 1:256 v = valid value the tcc prescaler counter is assigned to tcc (r1). the contents of the iocc1 register are cleared when one of the following occurs : ? a value is written to tcc register ? a value is written to tcc prescaler bits (bits 3, 2, 1, 0 of cont) ? power-on reset, /reset ? wdt time out reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 29 (this specification is subject to change without further notice) 6.2.20 iocd1 (lvd control register) bit 7 6 5 4 3 2 1 0 em78p342n/343n - - - - lvdie lvden lvd1 lvd0 ice342n type1 type0 lvr1 lvr0 lvdie lvden lvd1 lvd0 bits 7~6 (type 1 ~ type 0): type selection for em78p343n or em78p342n or EM78P341N or 108c. type 1, type 0 vdd reset level 11 em78p343n (default) (20pin) 10 em78p342n (18pin) 01 EM78P341N (14pin) 00 108c (8pin) bits 5~4 (lvr1 ~ lvr0): low voltage reset enable bits. lvr1, lvr0 vdd reset level vdd release level 11 na (power-on reset) 10 2.7v 2.9v 01 3.5v 3.7v 00 4.0v 4.2v note iocd1<3> register is both readable and writable individual interrupt is enabled by setting its associated control bit in the iocd1 <4> to "1" global interrupt is enabled by the eni instruction and is disabled by the disi instruction. refer to fig. 6-8 ( interrupt input circuit ) under section 6.6 ( interrupt ). bit 3 (lvdie): low voltage detector interrupt enable bit. 0 = disable low voltage detector interrupt. 1 = enable low voltage detector interrupt. when the detect low level voltage is used to enter an interrupt vector or enter next instruction, the lvdie bit must be set to ?enable?. bit 2 (lvden): low voltage detector enable bit 0 = low voltage detector disable 1 = low voltage detector enable bit 1~0 (lvd1:0): low voltage detector level bits. lvden lvd1,lvd0 lvd voltage interrupt level /lvd vdd 2.3v 0 1 11 vdd > 2.3v 1 vdd 3.3v 0 1 10 vdd > 3.3v 1 vdd 4.0v 0 1 01 vdd > 4.0v 1 vdd 4.5v 0 1 00 vdd > 4.5v 1 0 xx na 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 30 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.2.21 ioce1 (output sink select control register) bit 7 6 5 4 3 2 1 0 em78p342n/343n - timersc cpus idle hs3 hs2 hs1 hs0 ice342n wdtps timersc cpus idle hs3 hs2 hs1 hs0 bit 7 (wdtps): wdt time-out period selection bit. 0 : 4.5ms 1 : 18ms bit 6 (timersc): tcc, tcca, tccb, tccc clock sources select 0/1 fs/fm* fs: sub frequency for wdt internal rc time base fm: main-oscillator clock bit 5 (cpus): cpu oscillator source select, 0/1 sub-oscillator (fs) / main oscillator (fosc) when cpus=0, the cpu oscillator select sub-oscillator and the main oscillator is stopped. bit 4 (idle): idle mode enable bit. this bit will decide slep instruction which mode to go. 0 : idle=?0?+slep instruction sleep mode 1 : idle=?1?+slep instruction idle mode cpu operation mode green mode fosc:stop fs: oscillation cpu: using fs normal mode fosc:oscillation fs: oscillation cpu: using fosc idle mode fosc:stop fs: oscillation cpu: stop sleep mode fosc:stop fs: stop cpu: stop idle="1 "+slep idle="0" slep wake up external interrupt reset cpus="1" cpus="0" idle="1 "+slep wake up idle="0" +slep external interrupt code option hlfs=1 fig. 6-2 cpu operation mode bit 3 (hs3): output sink current select for p63 (not applicable for EM78P341N) bit 2 (hs2): output sink current select for p62 . (not applicable for EM78P341N) bit 1 (hs1): output sink current select for p61 . bit 0 (hs0): output sink current select for p60 . hsx vdd = 5v, sink current 0 20ma (in 0.3vdd) 1 90ma (in 0.3vdd) www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 31 (this specification is subject to change without further notice) 6.2.21 iocf1 (pull-high control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 /ph67 /ph66 /ph65 /ph64 /ph63 /ph62 /ph61 /ph60 note the iocd0 register is both readable and writable. bit 7 (/ph67): control bit is used to enable the pull-high of the p67 pin. 0 = enable internal pull-high 1 = disable internal pull-high bit 6 (/ph66): control bit used to enable the pull-high function of the p66 pin. bit 5 (/ph65): control bit used to enable the pull-high function of the p65 pin. (not applicable for EM78P341N) bit 4 (/ph64): control bit used to enable the pull-high function of the p64 pin. (not applicable for EM78P341N) bit 3 (/ph63): control bit used to enable the pull-high function of the p63 pin. (not applicable for EM78P341N) bit 2 (/ph62): control bit used to enable the pull-high function of the p62 pin. (not applicable for EM78P341N) bit 1 (/ph61): control bit used to enable the pull-high function of the p61 pin. bit 0 (/ph60): control bit used to enable the pull-high function of the p60 pin. 6.3 tcc/wdt and prescaler there are two 8-bit counters available as prescalers that can be extended to 16-bit counter for the tcc and wdt respectively. the pst2 ~ pst0 bits of the cont register are used to determine the ratio of the tcc prescaler, and the pwr2 ~ pwr0 bits of the ioce0 register are used to determine the wdt prescaler. the prescaler counter is cleared by the instructions each time such instructions are written into tcc. the wdt and prescaler will be cleared by the ?wdtc? and ?slep? instructions. fig. 6-1 (next page) depicts the block diagram of tcc/wdt. tcc (r1) is an 8-bit timer/counter. the tcc clock source can be internal clock or external signal input (edge selectable from the tcc pin). if tcc signal source is from an internal clock, tcc will be incremented by 1 at every instruction cycle (without prescaler). referring to fig. 6-1, clk=fosc/2 or clk=fosc/4 is dependent to the code option bit . clk=fosc/2 if the clks bit is "0," and clk=fosc/4 if the clks bit is "1." if the tcc signal source is from an external clock input, tcc will be incremented by 1 at every falling edge or rising edge of the tcc pin. the tcc pin input time length (kept at high or low level) must be greater than 1clk. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 32 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) note the internal tcc will stop running when in sleep mode. however, during ad conversion, when tcc is set to ?slep? instruction, if the adwe bit of the re register is enabled, tcc will keep on running. the watchdog timer is a free running on-chip rc oscillator. the wdt will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). during normal operation or in sleep mode, a wdt time-out (if enabled) will cause the device to reset. the wdt can be enabled or disabled any time during normal mode through software programming. refer to wdte bit of ioce0 register (section 6.2.10 ioce0 (wdt control & interrupt mask registers 2) . with no prescaler, the wdt time-out period is approximately 18ms 1 or 4.5ms 2 . 8-bit counter wdt prescaler 8 to 1 mux wdt time out wdte (ioce0) tcc pin mux clk (fosc/2 or fosc/4) 8-bit counter (iocc1) 8 to 1 mux te (cont) data bus tcc overflow interrupt ts (cont) sync 2 cycles tcc (r1) 0 1 psw2~0 (ioce0) prescaler psr2~0 (cont) fig. 6-3 tcc and wdt block diagram 1 vdd=5v, wdt time-out period = 16.5ms 30% vdd=3v, wdt time-out period = 18ms 30% 2 vdd=5v, wdt time-out period = 4.2ms 30% vdd=3v, wdt time-out period = 4.5ms 30% www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 33 (this specification is subject to change without further notice) 6.4 i/o ports the i/o registers (port 5, port 6, and port 7) are bidirectional tri-state i/o ports. port 5 is pulled-high and pulled-down internally by software. likewise, p6 has its open-drain output set through software. port 5 features an input status changed interrupt (or wake-up) function. each i/o pin can be defined as "input" or "output" pin by the i/o control register (ioc5 ~ ioc7). the i/o registers and i/o control registers are both readable and writable. the i/o interface circuits for port 5, port 6, and port 7 are illustrated in figures 6-4, 6-5, 6-6, & 6-7 (see next page). pcwr pcrd pdwr pdrd iod 0 1 m u x port q q _ d d q q _ clk p r c l clk p r c l note: open-drain is not shown in the figure. fig. 6-4 i/o port and i/o control register circuit for port 6 and port 7 pcrd iod pcwr pdwr pdrd bit 6 of ioce port m u x 0 1 clk clk clk p p p r r r c l l l c c q q q q q q d d d _ _ _ int note: open-drain is not shown in the figure. fig. 6-5 i/o port and i/o control register circuit for p60 (/int) www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 34 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) pcrd m u x iod 0 1 pdrd p50 ~ p57 pcwr d q q @ clk 1 3 $ - pdwr d q q @ clk 1 3 $ - 1 3 $ - clk dq q @ ti n port note: pull-high (down) is not shown in the figure. fig. 6-6 i/o port and i/o control register circuit for port 50 ~ p57 ti 1 ti 8 io c f.1 ti 0 rf.1 ?. fig. 6-7 port 5 block diagram with input change interrupt / wake-up www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 35 (this specification is subject to change without further notice) 6.4.1 usage of port 5 input change wake-up/interrupt function (1) wake-up (2) wake-up and interrupt (a) before sleep (a) before sleep 1. disable wdt 1. disable wdt 2. read i/o port 5 (mov r65r5) 2. read i/o port 5 (mov r5,r5) 3. execute "eni" or "disi" 3. execute "eni" or "disi" 4. enable wake-up bit (set re icwe =1) 4. enable wake-up bit (set re icwe =1) 5. execute "slep" instruction 5. enable interrupt (set iocf icie =1) (b) after wake-up 6. execute "slep" instruction next instruction (b) after wake-up 1. if "eni" interrupt vector (008h) 2. if "disi" next instruction (3) interrupt (a) before port 5 pin change 1. read i/o port 6 (mov r5,r5) 2. execute "eni" or "disi" 3. enable interrupt (set iocf icie =1) (b) after port 5 pin changed (interrupt) 1. if "eni" interrupt vector (006h) 2. if "disi" next instruction 6.5 reset and wake-up 6.5.1 reset and wake-up operation a reset is initiated by one of the following events : 1. power-on reset 2. /reset pin input "low" 3. wdt time-out (if enabled) the device is kept in reset condition for a period of approximately 18ms 3 (except in lxt mode) after the reset is detected. when in lxt mode, the reset time is 500ms. two choices (18ms 3 or 4.5ms 4 ) are available for wdt-time out period . once a reset occurs, the following functions are performed (the initial address is 000h) : ? the oscillator continues running, or will be started (if in sleep mode) ? the program counter (r2) is set to all "0" 3 vdd=5v, wdt time-out period = 16.5ms 30%. vdd=3v, wdt time-out period = 18ms 30%. 4 vdd=5v, wdt time-out period = 4.2ms 30%. vdd=3v, wdt time-out period = 4.5ms 30%. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 36 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) ? all i/o port pins are configured as input mode (high-impedance state) ? the watchdog timer and prescaler are cleared ? when power is switched on, the upper three bits of r3 is cleared ? the iocb0 register bits are set to all "1" ? the iocc0 register bits are set to all "1" ? the iocd0 register bits are set to all "1" ? bits 7, 5, and 4 of the ioce0 register are cleared ? bits 5 and 4 of the re register are cleared ? rf and iocf0 registers are cleared executing the ?slep? instruction will assert the sleep (power down) mode. while entering into sleep mode, the oscillator, tcc, tcca, tccb, and tccc are stopped. the wdt (if enabled) is cleared but keeps on running. during ad conversion, when ?slep? instruction is set; the oscillator, tcc, tcca, tccb, and tccc keep on running. the wdt (if enabled) is cleared but keeps on running. the controller can be awakened by: case 1 external reset input on /reset pin case 2 wdt time-out (if enabled) case 3 port 5 input status changes (if icwe is enabled) case 4 comparator output status changes (if cmpwe is enabled) case 5 ad conversion completed (if adwe is enabled) case 6 low voltage detector (if lvdwe is enabled) the first two cases (1 & 2) will cause the EM78P341N/342n/343n to reset. the t and p flags of r3 can be used to determine the source of the reset (wake-up). cases 3, 4, & 5 are considered the continuation of program execution and the global interrupt ("eni" or "disi" being executed) determines whether or not the controller branches to the interrupt vector following wake-up. if eni is executed before slep, the instruction will begin to execute from address 0x06 (case 3), 0x0f (case 4), and 0x0c (case 5) after wake-up. if disi is executed before slep, the execution will restart from the instruction next to slep after wake-up. only one of cases 2 to 5 can be enabled before entering into sleep mode. that is : case [a] if wdt is enabled before slep, all of the re bit is disabled. hence, the EM78P341N/342n/343n can be awakened only with case 1 or case 2. refer to the section on interrupt (section 6.6) for further details. case [b] if port 5 input status change is used to wake up EM78P341N/342n/343n and the icwe bit of the re register is enabled before slep, wdt must be disabled. hence, the EM78P341N/342n/343n can be awakened only with case 3. wake-up time is dependent on oscillator mode. in rc mode, wake-up time is 32 clocks (for stable oscillators). in high crystal mode, wake-up time is 2ms and 32 clocks (for stable oscillators), and in low crystal mode, wake-up time is 500ms. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 37 (this specification is subject to change without further notice) case [c] if the comparator output status change is used to wake-up the em78p342n/ 343n and the cmpwe bit of the re register is enabled before slep, wdt must be disabled by software. hence, the em78p342n/343n can be awakened only with case 4. wake-up time is dependent on oscillator mode. in rc mode the wake-up time is 32 clocks (for stable oscillators). in high crystal mode, wake-up time is 2ms and 32 clocks (for stable oscillators), and in low crystal mode, wake-up time is 500ms. case [d] if ad conversion completed is used to wake-up the EM78P341N/342n/343n and adwe bit of re register is enabled before slep, wdt must be disabled by software. hence, the EM78P341N342n/343n can be awakened only with case 5. the wake-up time is 15 tad (adc clock period). case[e] if low voltage detector is used to wake-up the EM78P341N/342n/343n and the lvdwe bit of bank 0-re register is enabled before slep, wdt must be disabled by software. hence, the EM78P341N/342n/343n can be awakened only with case 6. wake-up time is dependent on oscillator mode. if port 5 input status change interrupt is used to wake up the EM78P341N/342n/343n (as in case [b] above), the following instructions must be executed before slep: bc r3, 7 ; select segment 0 mov a, @00xx1110b ; select wdt prescaler and disable wdt iow ioce0 wdtc ; clear wdt and prescaler mov r5, r5 ; read port 5 eni (or disi) ; enable (or disable) global interrupt mov a, @xxxxxx1xb ; enable port 5 input change wake-up bit mov re mov a, @xxxxxx1xb ; enable port 5 input change interrupt iow iocf0 slep ; sleep similarly, if the comparator interrupt is used to wake up the EM78P341N/342n/343n (as in case [c] above), the following instructions must be executed before slep: bc r3, 7 ; select segment 0 mov a, @xxx10xxxb ; select a comparator and p64 functions as co pin iow ioc80 mov a, @00x11110b ; select wdt prescaler and disable wdt, and enable comparator output status change interrupt iow ioce0 wdtc ; clear wdt and prescaler eni (or disi) ; enable (or disable) global interrupt mov a, @xxx0x1xxb ; enable comparator output status change wake-up bit mov re slep ; sleep www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 38 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.5.1.1 wake-up and interrupt modes operation summary the controller can be awakened from sleep mode and idle mode. the wake-up signals are listed as follows. wakeup signal sleep mode idle mode green mode normal mode external interrupt wake-up + interrupt (if interrupt is enabled) + next instruction interrupt (if interrupt is enabled) or next instruction interrupt (if interrupt is enabled) or next instruction port 5 pin change if enable icwe bit wake-up + interrupt (if interrupt is enabled) + next instruction if enable icwe bit wake-up + interrupt (if interrupt is enabled) + next instruction interrupt (if interrupt is enabled) or next instruction interrupt (if interrupt is enabled) or next instruction tcc overflow interrupt x wake-up + interrupt (if interrupt is enabled) + next instruction interrupt (if interrupt is enabled) or next instruction interrupt (if interrupt is enabled) or next instruction ad conversion complete interrupt if enable adwe bit wake-up + interrupt (if interrupt is enabled) + next instruction fs and fm don?t stop if enable adwe bit wake-up + interrupt (if interrupt enable) + next instruction fs and fm don?t stop fs and fm don?t stop interrupt (if interrupt is enabled) or next instruction comparator interrupt if enable cmpwe bit wake-up + interrupt (if interrupt enable) + next instruction if enable cmpwe bit wake-up + interrupt (if interrupt enable) + next instruction interrupt (if interrupt enable) or next instruction interrupt (if interrupt enable) or next instruction high-pulse width timer underflow interrupt x wake-up + interrupt (if interrupt enable) + next instruction interrupt (if interrupt enable) or next instruction interrupt (if interrupt enable) or next instruction low-pulse width timer underflow interrupt x wake-up + interrupt (if interrupt enable) + next instruction interrupt (if interrupt enable) or next instruction interrupt (if interrupt enable) or next instruction tcca overflow interrupt x wake-up + interrupt (if interrupt enable) + next instruction interrupt (if interrupt enable) or next instruction interrupt (if interrupt enable) or next instruction tccb overflow interrupt x wake-up + interrupt (if interrupt enable) + next instruction interrupt (if interrupt enable) or next instruction interrupt (if interrupt enable) or next instruction tccc overflow interrupt x wake-up + interrupt (if interrupt enable) + next instruction interrupt (if interrupt enable) or next instruction interrupt (if interrupt enable) or next instruction low voltage detector interrupt if enable lvdwe bit wake-up + interrupt (if interrupt enable) + next instruction if enable lvdwe bit wake-up + interrupt (if interrupt enable) + next instruction interrupt (if interrupt enable) or next instruction interrupt (if interrupt enable) or next instruction wdt time out reset reset reset reset low voltage reset reset reset reset reset after wake up: 1. if interrupt is enabled interrupt+ next instruction 2. if interrupt is disabled next instruction www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 39 (this specification is subject to change without further notice) signal sleep mode idle mode normal mode green mode disi+iocf0(exie) bit 2 =1 disi + iocf0 (exie) bit 2=1 disi + iocf0 (exie) bit 2=1 wake-up + next instruction set rf (exif)=1 next instruction + set rf (exif)=1 next instruction + set rf (exif)=1 eni + iocf0(exie) bit 2 =1 eni + iocf0 (exie) bit 2=1 eni + iocf0 (exie) bit 2=1 int pin na wake-up + interrupt vector (003h) + set rf (exif)=1 interrupt vector (003h) + set rf (exif)=1 interrupt vector (003h) + set rf (exif)=1 re (icwe) bit 1=0, iocf0 (icie) bit 1=0 re (icwe) bit 1=0, iocf0 (icie) bit 1=0 iocf0 (icie) bit 1=0 iocf0 (icie) bit 1=0 oscillator, tcc, tccx and ir/pwm are stopped. port 5 input status changed wake-up is invalid. oscillator, tc c, tccx and ir/pwm keep on running. port5 input status changed wake-up is invalid. port 5 input status change interrupted is invalid port 5 input status change interrupted is invalid re (icwe) bit 1=0, iocf0 (icie) bit 1=1 re (icwe) bit 1=0, iocf0 (icie) bit 1=1 n/a n/a set rf (icif)=1, oscillator, tcc, tccx and ir/pwm are stopped. port 5 input status changed wake-up is invalid. set rf (icif)=1, oscillator, tc c, tccx and ir/pwm keep on running. port5 input status changed wake-up is invalid. n/a n/a re (icwe) bit 1=1, iocf0 (icie) bit 1=0 re (icwe) bit 1=1, iocf0 (icie) bit1=0 n/a n/a wake-up + next instruction oscillator, tcc, tccx and ir/pwm are stopped. wake-up + next instruction oscillator, tc c, tccx and ir/pwm keep on running. n/a n/a re (icwe) bit1=1, disi + iocf0 (icie) bit 1=1 re (icwe) bit 1=1, disi + iocf0 (icie) bit 1=1 disi + iocf0 (icie) bit 1=1 disi + iocf0 (icie) bit 1=1 wake-up + next instruction + set rf (icif)=1 oscillator, tcc, tccx and ir/pwm are stopped. wake-up + next instruction + set rf (icif)=1 oscillator, tc c, tccx and ir/pwm keep on running. next instruction + set rf (icif)=1 next instruction + set rf (icif)=1 re (icwe) bit 1=1, eni + iocf0 (icie) bit 1=1 re (icwe) bit 1=1, eni + iocf0 (icie) bit 1=1 eni + iocf0 (icie) bit 1=1 eni + iocf0 (icie) bit 1=1 port 5 input status change wake-up + interrupt vector (006h) + set rf (icif)=1 oscillator, tcc, tccx and ir/pwm are stopped. wake-up + interrupt vector (006h) + set rf (icif)=1 oscillator, tc c, tccx and ir/pwm keep on running. interrupt vector(006h) + set rf (icif)=1 interrupt vector(006h) + set rf (icif)=1 disi+iocf0(tcie) bit 0 =1 disi + iocf0 (tcie) bit 0=1 disi + iocf0 (tcie) bit 0=1 wake-up + next instruction set rf (tcif)=1 next instruction + set rf (tcif)=1 next instruction + set rf (tcif)=1 eni + iocf0(tcie) bit 0 =1 eni + iocf0 (tcie) bit 0=1 eni + iocf0 (tcie) bit 0=1 tcc over flow na wake-up + interrupt vector (009h) + set rf (tcif)=1 interrupt vector (009h) + set rf (tcif)=1 interrupt vector (009h) + set rf (tcif)=1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 40 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) signal sleep mode idle mode normal mode green mode re (adwe) bit 3=0, ioce0 (adie) bit 5=0 re (adwe) bit 3=0, ioce0 (adie) bit 5=0 ioce0 (adie) bit 5=0 ioce0 (adie) bit 5=0 clear r9 (adrun)=0, adc is stopped, ad conversion wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. clear r9 (adrun)=0, adc is stopped, ad conversion wake-up is invalid. oscillator, tc c, tccx and ir/pwm keep on running. ad conversion interrupted is invalid ad conversion interrupted is invalid re (adwe) bit 3=0, ioce0 (adie) bit 5=1 re (adwe) bit 3=0, ioce0 (adie) bit 5=1 n/a n/a set rf (adif)=1, r9 (adrun)=0, adc is stopped, ad conversion wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. set rf (adif)=1, r9 (adrun)=0, adc is stopped, ad conversion wake-up is invalid. oscillator, tc c, tccx and ir/pwm keep on running. n/a n/a re (adwe) bit 3=1, ioce0 (adie) bit 5=0 re (adwe) bit 3=1, ioce0 (adie) bit 5=0 n/a n/a wake-up + next instruction, oscillator, tcc, tccx and ir/pwm keep on running. wake-up when adc completed. wake-up + next instruction, oscillator, tc c, tccx and ir/pwm keep on running. wake-up when adc completed. n/a n/a re (adwe) bit 3=1, disi + ioce0 (adie) bit 5=1 re (adwe) bit 3=1, disi + ioce0 (adie) bit 5=1 disi + ioce0 (adie) bit 5=1 disi + ioce0 (adie) bit 5=1 wake-up + next instruction + re (adif)=1, oscillator, tcc, tccx and ir/pwm keep on running. wake-up when adc completed. wake-up + next instruction + re (adif)=1, oscillator, tc c, tccx and ir/pwm keep on running. wake-up when adc completed. next instruction + re (adif)=1 next instruction + re (adif)=1 re (adwe) bit 3=1, eni + ioce0 (adie) bit 5=1 re (adwe) bit 3=1, eni + ioce0 (adie) bit 5=1 eni + ioce0 (adie) bit 5=1 eni + ioce0 (adie) bit 5=1 ad conversion wake-up + interrupt vector (00ch)+ re (adif)=1, oscillator, tcc, tccx and ir/pwm keep on running. wake-up when adc completed. wake-up + interrupt vector (00ch)+ re (adif)=1, oscillator, tc c, tccx and ir/pwm keep on running. wake-up when adc completed. interrupt vector (00ch) + set re (adif)=1 interrupt vector (00ch) + set re (adif)=1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 41 (this specification is subject to change without further notice) signal sleep mode idle mode normal mode green mode re (cmpwe) bit 2=0, ioce0 (cmpie) bit 4=0 re (cmpwe) bit 2=0, ioce0 (cmpie) bit 4=0 ioce0 (cmpie) bit 4=0 ioce0 (cmpie) bit 4=0 comparator output status changed wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. comparator output status changed wake-up is invalid. oscillator, tc c, tccx and ir/pwm keep on running. comparator output status change interrupt is invalid. comparator output status change interrupt is invalid. re (cmpwe) bit 2=0, ioce0 (cmpie) bit 4=1 re (cmpwe) bit 2=0, ioce0 (cmpie) bit 4=1 n/a n/a set re (cmpif)=1, comparator output status changed wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. set re (cmpif)=1, comparator output status changed wake-up is invalid. oscillator, tc c, tccx and ir/pwm keep on running. n/a n/a re (cmpwe) bit 2=1, ioce0 (cmpie) bit 4=0 re (cmpwe) bit 2=1, ioce0 (cmpie) bit 4=0 n/a n/a wake-up + next instruction, oscillator, tcc, tccx and ir/pwm are stopped. wake-up + next instruction, oscillator, tc c, tccx and ir/pwm keep on running. n/a n/a re (cmpwe) bit 2=1, disi + ioce0 (cmpie) bit 4=1 re (cmpwe) bit 2=1, disi + ioce0 (cmpie) bit 4=1 disi + ioce0 (cmpie) bit 4=1 disi + ioce0 (cmpie) bit 4=1 wake-up + next instruction + set re (cmpif)=1, oscillator, tcc, tccx and ir/pwm are stopped. wake-up + next instruction + set re (cmpif)=1, oscillator, tc c, tccx and ir/pwm keep on running. next instruction + set re (cmpif)=1 next instruction + set re (cmpif)=1 re (cmpwe) bit 2=1, eni + ioce0 (cmpie) bit 4=1 re (cmpwe) bit 2=1, eni + ioce0 (cmpie) bit 4=1 eni + ioce0 (cmpie) bit 4=1 eni + ioce0 (cmpie) bit 4=1 comparator (comparator output status change) wake-up + interrupt vector (00fh) + set re (cmpif)=1,oscillator, tcc, tccx and ir/pwm are stopped. wake-up + interrupt vector (00fh) + set re (cmpif)=1,oscillator, tcc, tccx and ir/pwm keep on running. interrupt vector (00fh) + set re (cmpif)=1 interrupt vector (00fh) + set re (cmpif)=1 disi + iocf0 (hpwtie) bit 6=1 disi + iocf0 (hpwtie) bit 6=1 disi + iocf0 (hpwtie) bit 6=1 wake-up +next instruction + set rf (hpwtif)=1 next instruction + set rf (hpwtif)=1 next instruction + set rf (hpwtif)=1 eni + iocf0 (hpwtie) bit 6 =1 eni + iocf0 (hpwtie) bit 6 =1 eni + iocf0 (hpwtie) bit 6 =1 ir/pwm underflow interrupt (high-pulse width timer underflow interrupt) n/a wake-up +interrupt vector (012h) + set rf (hpwtif)=1 interrupt vector (012h) + set rf (hpwtif)=1 interrupt vector (012h) + set rf (hpwtif)=1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 42 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) signal sleep mode idle mode normal mode green mode disi + iocf0 (lpwtie) bit 7=1 disi + iocf0 (lpwtie) bit 7=1 disi + iocf0 (lpwtie) bit 7=1 wake-up +next instruction + set rf (lpwtif)=1 next instruction + set rf (lpwtif)=1 next instruction + set rf (lpwtif)=1 eni + iocf0 (lpwtie) bit 7 =1 eni + iocf0 (lpwtie) bit 7 =1 eni + iocf0 (lpwtie) bit 7 =1 ir/pwm underflow interrupt (low-pulse width timer underflow interrupt) n/a wake-up +interrupt vector (015h) + set rf (lpwtif)=1 interrupt vector (015h) + set rf (lpwtif)=1 interrupt vector (015h) + set rf (lpwtif)=1 disi + iocf0 (tccaie) bit 3=1 disi + iocf0 (tccaie) bit 3=1 disi + iocf0 (tccaie) bit 3=1 wake-up +next instruction + set rf (tccaif)=1 next instruction + set rf (tccaif)=1 next instruction + set rf (tccaif)=1 eni + iocf0 (tccaie) bit 3=1 eni + iocf0 (tccaie) bit 3=1 eni + iocf0 (tccaie) bit 3=1 tcca over flow n/a wake-up +interrupt vector (018h) + set rf (tccaif)=1 interrupt vector (018h) + set rf (tccaif)=1 interrupt vector (018h) + set rf (tccaif)=1 disi + iocf0 (tccbie) bit 4=1 disi + iocf0 (tccbie) bit 4=1 disi + iocf0 (tccbie) bit 4=1 wake-up +next instruction + set rf (tccbif)=1 next instruction + set rf (tccbif)=1 next instruction + set rf (tccbif)=1 eni + iocf0 (tccbie) bit 4=1 eni + iocf0 (tccbie) bit 4=1 eni + iocf0 (tccbie) bit 4=1 tccb over flow n/a wake-up +interrupt vector (01bh) + set rf (tccbif)=1 interrupt vector (01bh) + set rf (tccbif)=1 interrupt vector (01bh) + set rf (tccbif)=1 disi + iocf0 (tcccie) bit 5=1 disi + iocf0 (tcccie) bit 5=1 disi + iocf0 (tcccie) bit 5=1 wake-up +next instruction + set rf (tcccif)=1 next instruction + set rf (tcccif)=1 next instruction + set rf (tcccif)=1 eni + iocf0 (tcccie) bit 5=1 eni + iocf0 (tcccie) bit 5=1 eni + iocf0 (tcccie) bit 5=1 tccc over flow n/a wake-up +interrupt vector (01eh) + set rf (tcccif)=1 interrupt vector (01eh) + set rf (tcccif)=1 interrupt vector (01eh) + set rf (tcccif)=1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 43 (this specification is subject to change without further notice) signal sleep mode idle mode normal mode green mode re (lvdwe) bit 0=0, iocd1 (lvdie) bit 3=0 re (lvdwe) bit 0=0, iocd1 (lvdie) bit 3=0 iocd1 (lvdie) bit 3=0 iocd1 (lvdie) bit 3=0 low voltage detector wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. low voltage detector wake-up is invalid. oscillator, tc c, tccx and ir/pwm keep on running. low voltage detector interrupted is invalid. low voltage detector interrupted is invalid. re (lvdwe) bit 0=0, iocd1 (lvdie) bit 3=1 re (lvdwe) bit 0=0, iocd1 (lvdie) bit 3=1 n/a n/a set re (lvdif)=1, low voltage detector wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. set re (lvdif)=1, low voltage detector wake-up is invalid. oscillator, tc c, tccx and ir/pwm keep on running. n/a n/a re (lvdwe) bit 0=1, iocd1 (lvdie) bit 3=0 re (lvdwe) bit 0=1, iocd1 (lvdie) bit 3=0 n/a n/a wake-up + next instruction, oscillator, tcc, tccx and ir/pwm are stopped. wake-up + next instruction, oscillator, tc c, tccx and ir/pwm keep on running. n/a n/a re (lvdwe) bit =1, disi + iocd1 (lvdie) bit 3=1 re (lvdwe) bit 0=1, disi + iocd1 (lvdie) bit 3=1 disi + iocd1 (lvdie) bit 3=1 disi + iocd1 (lvdie) bit 3=1 wake-up + next instruction + set re (lvdif)=1, oscillator, tcc, tccx and ir/pwm are stopped. wake-up + next instruction + set re (lvdif)=1, oscillator, tc c, tccx and ir/pwm keep on running. next instruction + set re (lvdif)=1 next instruction + set re (lvdif)=1 re (lvdwe) bit 2=1, eni + iocd1 (lvdie) bit 3=1 re (lvdwe) bit0=1, eni + iocd1 (lvdie) bit 3=1 eni + iocd1 (lvdie) bit 3=1 eni + iocd1 (lvdie) bit 3=1 low voltage detector interrupt wake-up + interrupt vector (021h) + set re (lvdif)=1,oscillator, tcc, tccx and ir/pwm are stopped. wake-up + interrupt vector (021h) + set re (lvdif)=1,oscillator, tcc, tccx and ir/pwm keep on running. interrupt vector (021h) + set re (lvdif)=1 interrupt vector (021h) + set re (lvdif)=1 wdt time out ioce (wdte) bit 7=1 wake-up + reset (address 0x00) wake-up + reset (address 0x00) reset (address 0x00) reset (address 0x00) low voltage reset wake-up + reset (address 0x00) wake-up + reset (address 0x00) reset (address 0x00) reset (address 0x00) www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 44 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.5.1.2 register initial values after reset the following summarizes the registers initialized values. address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name c57 c56 c55 c54 c53 c52 c51 c50 type 108c 341n 342n 343n 108c 341n 342n 343n ? 108c 341n 342n 343n 108c 341n 342n 343n 108c 341n 342n 343n ? ? power-on 0 10 11 0 10 10 1 1 1 /reset and wdt 0 10 11 0 10 10 1 1 1 n/a ioc50 wake-up from pin change 0 p0 pp 0 p0 p0 p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 type ? 108c 341n 342n 343 n 108c 341n 342n 343n 108c 341n 342n 343n 108c 341n 342n 343n 108c 341n 342n 343n 108c 341n 342n 343n 108c 341n 342n 343n power-on 1 0 10 10 10 10 1 0 1 0 1 /reset and wdt 1 0 10 10 10 10 1 0 1 0 1 n/a ioc60 wake-up from pin change p 0 p0 p0 p0 p0 p 0 p 0 p bit name x x x x x x c71 c70 power-on 0 0 0 0 0 0 1 1 /reset and wdt 0 0 0 0 0 0 1 1 n/a ioc70 wake-up from pin change p p p p p p p p bit name x x cmpout cos1 cos0 tccaen tccats tccate power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc80 wake-up from pin change p p p p p p p p bit name tccbhe tccben tccbts tccbte x tcccen tcccts tcccte power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc90 wake-up from pin change p p p p p p p p bit name tcccse tcccs2 tcccs1 tcccs0 ire hf lgp iroute power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioca0 (ir cr) wake-up from pin change p p p p p p p p bit name /pd57 /pd56 /pd55 /pd54 /pd53 /pd52 /pd51 /pd50 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a iocb0 (pdcr) wake-up from pin change p p p p p p p p www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 45 (this specification is subject to change without further notice) address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name /od67 /od66 /od65 /od64 /od63 /od62 /od61 /od60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a iocc0 (odcr) wake-up from pin change p p p p p p p p bit name /ph57 /ph56 /ph55 /ph54 /ph53 /ph52 /ph51 /ph50 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a iocd0 (phcr1) wake-up from pin change p p p p p p p p bit name wdtc eis adie cmpie pswe psw2 psw1 psw0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioce0 wake-up from pin change p p p p p p p p bit name lpwtie hpwtie tcccie tccbie tccaie exie icie tcie power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a iocf0 wake-up from pin change p p p p p p p p bit name tcca7 tcca6 tcca5 tcca4 tcca3 tcca2 tcca1 tcca0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc51 (tcca) wake-up from pin change p p p p p p p p bit name tccb7 tccb6 tccb5 tccb4 tccb3 tccb2 tccb1 tccb0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc61 (tccb) wake-up from pin change p p p p p p p p bit name tccbh7 tccbh6 tccbh5 tccbh4 tccbh3 tccbh2 tccbh1 tccbh 0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc71 (tccbh) wake-up from pin change p p p p p p p p bit name tccc7 tccc6 tccc5 tccc4 tccc3 tccc2 tccc1 tccc0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc81 (tccc) wake-up from pin change p p p p p p p p bit name ltr7 ltr6 ltr5 ltr4 ltr3 ltr2 ltr1 ltr0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc91 (ltr) wake-p from pin change p p p p p p p p www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 46 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name htr7 htr6 htr5 htr4 htr3 htr2 htr1 htr0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioca1 (htr) wake-up from pin change p p p p p p p p bit name htse hts2 hts1 hts0 ltse lts2 lts1 lts0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a iocb1 (hlts) wake-up from pin change p p p p p p p p bit name tccpc7 tccpc6 tccpc5 tccpc4 tccpc3 tccpc2 tccpc1 tccpc 0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a iocc1 (tccpc) wake-up from pin change p p p p p p p p bit name type1 type0 lvr1 lvr0 lvdie lvden lvd1 lvd0 power-on 1 1 1 1 0 0 1 1 /reset and wdt p p p p 0 p 1 1 n/a iocd1 (lvd cr) (romless) wake-up from pin change p p p p p p p p hs1 wdpts timers c cpus idle hs3 hs2 hs1 hs0 power-on 1 1 1 1 0 0 0 0 /reset and wdt p 1 1 1 0 0 0 0 n/a ioce1 (hsc) (romless) wake-up from pin change p p p p p p p p bit name /ph67 /ph66 /ph65 /ph64 /ph63 /ph62 /ph61 /ph60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a iocf1 (phcr2) wake-up from pin change p p p p p p p p bit name inte int ts te pste pst2 pst1 pst0 power-on 1 0 1 1 0 0 0 0 /reset and wdt 1 0 1 1 0 0 0 0 n/a cont wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? ? ? power-on u u u u u u u u /reset and wdt p p p p p p p p 0x00 r0(iar) wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? ? ? power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 00 0 0x01 r1(tcc) wake-up from pin change p p p p p p p p www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 47 (this specification is subject to change without further notice) address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name ? ? ? ? ? ? ? ? power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x02 r2 (pc) wake-up from pin change jump to address 0x06 or continue to execute next instruction bit name rst iocs ps0 t p z dc c power-on 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p 0x03 r3 (sr) wake-up from pin change p p p t t p p p bit name x bs x x x x x x power-on 0 0 u u u u u u /reset and wdt 0 0 p p p p p p 0x04 r4 (rsr) wake-up from pin change 0 p p p p p p p bit name p57 p56 p55 p54 p53 p52 p51 p50 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x05 r5 wake-up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x06 r6 wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? p71 p70 power-on 0 0 0 0 0 0 1 1 /reset and wdt 0 0 0 0 0 0 1 1 0x7 r7 wake-up from pin change p p p p p p p p bit name ? ? ? ? ade3 ade2 ade1 ade0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x8 r8 (aisr) wake-up from pin change 0 0 0 0 p p p p bit name vrefs ckr1 ckr0 adrun adpd ? adis1 adis0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x9 r9 (adcon) wake-up from pin change p p p p p 0 p p bit name cali sign vof[2] vof[1] vof[0] ? ? ? power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0xa ra (adoc) wake-up from pin change p p p p p p p p www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 48 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 power-on u u u u u u u u /reset and wdt u u u u u u u u 0xb rb (addata) wake-up from pin change p p p p p p p p bit name ?0? ?0? ?0? ?0? ad11 ad10 ad9 ad8 power-on 0 0 0 0 u u u u /reset and wdt 0 0 0 0 u u u u 0xc rc (addata1h) wake-up from pin change 0 0 0 0 p p p p bit name ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 power-on u u u u u u u u /reset and wdt u u u u u u u u 0xd rd (addata1l0) wake-up from pin change p p p p p p p p bit name ?- ? adif cmpif adwe cmpwe icwe ? power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0xe re (isr2) wake-up from pin change p p p p p p p p bit name lpwtif hpwtif tcccif tccbif tccaif exif icif tcif power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0xf rf (isr1) wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? ? ? power-on u u u u u u u u /reset and wdt p p p p p p p p 0x10~0x3f r10~r3f wake-up from pin change p p p p p p p p legend: ? ? ? = not used ?p? = previous value before reset ?u? = unknown or don?t care ?t? = check ?reset type? table in section 6.5.2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 49 (this specification is subject to change without further notice) 6.5.1.3 controller reset block diagram wdt timeout oscillator d q clk clr wdt vdd setup time reset clk /reset power-on reset voltage detector enwdtb fig. 6-8 controller reset block diagram 6.5.2 the t and p status u nder status (r3) register a reset condition is initiated by one of the following events : 1. power-on reset 2. /reset pin input "low" 3. wdt time-out (if enabled) the values of rst, t, and p as listed in the table below, are used to check how the processor wakes up. reset type rst t p power-on 0 1 1 /reset during operating mode 0 * p * p /reset wake-up during sleep mode 0 1 0 wdt during operating mode 0 0 1 wdt wake-up during sleep mode 0 0 0 wake-up on pin change during sleep mode 1 1 0 * p : previous status before reset the following shows the events that may affect the status of t and p. event rst t p power-on 0 1 1 wdtc instruction * p 1 1 wdt time-out 0 0 * p slep instruction * p 1 0 wake-up on pin changed during sleep mode 1 1 0 * p: previous value before reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 50 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.6 interrupt the EM78P341N/342n/343n has six interrupts as listed below : 1. tcc, tcca, tccb, tccc overflow interrupt 2. port 5 input status change interrupt 3. external interrupt [(p60, /int) pin] 4. analog to digital conversion completed 5. ir/pwm underflow interrupt 6. when the comparators status changes (not applicable to EM78P341N) 7. low voltage detector interrupt before the port 5 input status change interrupt is enabled, reading port 5 (e.g. "mov r5,r5") is necessary. each port 5 pin will have this feature if its status changes. the port 5 input status change interrupt will wake up the EM78P341N/342n/343n from sleep mode if it is enabled prior to going into sleep mode by executing slep instruction. when wake up occurs, the controller will continue to execute program in-line if the global interrupt is disabled. if enabled, the global interrupt will branch out to the interrupt vector 006h. external interrupt equipped with digital noise rejection circuit (input pulse less than system clock time) is eliminated as noise. however, under low crystal oscillator (lxt) mode the noise rejection circuit will be disabled. edge selection is possible with inte of cont. when an interrupt is generated by the external interrupt (when enabled), the next instruction will be fetched from address 003h. refer to the word 1 bits 9 & 8 (section 6.14.2, code option register (word 1)) for digital noise rejection definition. rf and re are the interrupt status register that records the interrupt requests in the relative flags/bits. iocf0 and ioce0 are interrupt mask registers. the global interrupt is enabled by the eni instruction and is disabled by the disi instruction. once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in rf. the interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. the flag (except for the icif bit) in the interrupt status register (rf) is set regardless of the eni execution. note that the result of rf will be the logic and of rf and iocf0 (refer to figure below). the reti instruction ends the interrupt routine and enables the global interrupt (the eni execution). when an interrupt is generated by the timer clock/counter (when enabled), the next instruction will be fetched from address 009, 018, 01b, and 01eh (tcc, tcca, tccb, and tccc respectively). when an interrupt generated by the ad conversion is completed (when enabled), the next instruction will be fetched from address 00ch. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 51 (this specification is subject to change without further notice) when an interrupt is generated by the high time / low time down counter underflow (when enabled), the next instruction will be fetched from addresses 012 and 015h (high time and low time respectively). when an interrupt is generated by the comparators (when enabled), the next instruction will be fetched from address 00fh (comparator interrupt). when an interrupt is generated by the low voltage detect (when enabled), the next instruction will be fetched from address 021 (low voltage detector interrupt). before an interrupt subroutine is executed, the contents of acc and the r3 and r4 registers are saved first by the hardware. if another interrupt occurs, the acc, r3, and r4 will be replaced by the new interrupt. after an interrupt service routine is completed, the acc, r3, and r4 registers are restored. int eni/disi iod rfwr iocfrd iocfwr irqn irqm rfrd iocf /reset /irqn vcc rf clk clk q q d p r l c _ p r l c q q _ d fig. 6.9 interrupt input circuit interrupt sources interrupt occurs eni/disi stack acc sack r3 reti acc r3 r4 stack r4 fig. 6.10 interrupt backup diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 52 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) in EM78P341N/342n/343n, each individual interrupt source has its own interrupt vector as depicted in the table below. interrupt vector interrupt status priority* 003h external interrupt 2 006h port 5 pin change 3 009h tcc overflow interrupt 4 00ch ad conversion complete interrupt 5 00fh comparator interrupt 6 012h high-pulse width timer underflow interrupt 7 015h low-pulse width timer underflow interrupt 8 018h tcca overflow interrupt 9 01bh tccb overflow interrupt 10 01eh tccc overflow interrupt 11 021h low voltage detector interrupt 1 * priority : 1 = highest ; 11 = lowest priority note comparator interrupt is not applicable to EM78P341N. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 53 (this specification is subject to change without further notice) 6.7 analog-to-digital converter (adc) the analog-to-digital circuitry consist of a 4-bit analog multiplexer; three control registers (aisr/r8, adcon/r9, & adoc/ra), three data registers (addata/rb, addata1h/rc, & addata1l/rd), and an adc with 12-bit resolution as shown in the functional block diagram below. the analog reference voltage (vref) and the analog ground are connected via separate input pins. the adc module utilizes successive approximation to convert the unknown analog signal into a digital value. the result is fed to the addata, addata1h, and addata1l. input channels are selected by the analog input multiplexer via the adcon register bits adis1 and adis0. addata1h data bus vref power-down fsco internal rc 4-1 mux 7 ~ 0 3 4 adc ( successive approximation ) 3 5 6 adcon rf aisr adcon start to convert 0 1 adcon " o b m p h 4 x j u d i 0 1 2 3 4 5 6 7 8 9 10 11 addata1l adc3 adc2 adc1 adc0 adc7 adc6 adc5 adc4 fig. 6-11 analog-to-digital conversion functional block diagram 6.7.1 adc control register (aisr/r8, adcon/r9, adoc/ra) 6.7.1.1 r8 (aisr: adc input select register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 aisr register defines the p5, p6, p7 pins as analog inputs or as digital i/o, individually. bit 7 (ade7): ad converter enable bit of p57 pin 0 = disable adc7, p57 functions as i/o pin 1 = enable adc7 to function as analog input pin bit 6 (ade6): ad converter enable bit of p55 pin 0 = disable adc6, p55 functions as i/o pin 1 = enable adc6 to function as analog input pin bit 5 (ade5): ad converter enable bit of p70 pin 0 = disable adc5, p70 functions as i/o pin 1 = enable adc5 to function as analog input pin www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 54 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) bit 4 (ade4): ad converter enable bit of p67 pin 0 = disable adc4, p67 functions as i/o pin 1 = enable adc4 to function as analog input pin bit 3 (ade3): ad converter enable bit of p53 pin 0 = disable adc3, p53 functions as i/o pin 1 = enable adc3 to function as analog input pin bit 2 (ade2): ad converter enable bit of p52 pin 0 = disable adc2, p53 functions as i/o pin 1 = enable adc2 to function as analog input pin bit 1 (ade1): ad converter enable bit of p51 pin 0 = disable adc1, p51 functions as i/o pin 1 = enable adc1 to function as analog input pin bit 0 (ade0): ad converter enable bit of p50 pin 0 = disable adc0, p50 functions as i/o pin 1 = enable adc0 to function as analog input pin 6.7.1.2 r9 (adcon: ad control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrefs ckr1 ckr0 adrun adpd adis2 adis1 adis0 the adcon register controls the operation of the ad conversion and decides which pin should be currently active. bit 7(vrefs): the input source of the adc vref 0 = the adc vref is connected to vdd (default value), and the vref/tcc/p54 pin carries out the p54 function 1 = the adc vref is connected to vref/tcc/p54 note the p54/tcc/vref pin cannot be applied to tcc and vref at the same time. if p54/tcc/vref functions as vref analog input pin, then cont bit 5 (ts) must be ?0?. the p54/tcc/vref pin priority is as follows: p54/tcc/vref pin priority high medium low vref tcc p54 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 55 (this specification is subject to change without further notice) bit 6 & bit 5 (ckr1 & ckr0): the prescaler of adc oscillator clock rate 00 = 1 : 16 (default value) 01 = 1 : 4 10 = 1 : 64 11 = 1 : 8 cpus ckr1: ckr0 operation mode max. operation frequency 1 00 fosc/16 4mhz 1 01 fosc/4 1mhz 1 10 fosc/64 16mhz 1 11 fosc/8 2mhz 0 internal rc ? bit 4 (adrun): adc starts to run 1 = an ad conversion is started. this bit can be set by software. 0 = reset upon completion of the conversion. this bit cannot be reset through software bit 3 (adpd): adc power-down mode. 1 = adc is operating 0 = switch off the resistor reference to save power even while the cpu is operating. bit 2 ~ bit 0 (adis2 ~ adis0): analog input select 000 = adin0/p50 001 = adin1/p51 010 = adin2/p52 011 = adin3/p53 100 = adin0/p67 101 = adin1/p70 110 = adin2/p55 111 = adin3/p57 these bits can only be changed when the adif bit and the adrun bit are both low. 6.7.1.3 ra (adoc: ad offset calibration register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cali sign vof[2] vof[1] vof[0] ? ? ? bit 7 (cali): calibration enable bit for adc offset 0 = disable calibration 1 = enable calibration bit 6 (sign): polarity bit of offset voltage 0 = negative voltage 1 = positive voltage www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 56 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) bit 5 ~ bit 3 (vof[2] ~ vof[0]): offset voltage bits vof[2] vof[1] vof[0] em78p342n/343n ice342n 0 0 0 0lsb 0lsb 0 0 1 2lsb 2lsb 0 1 0 4lsb 4lsb 0 1 1 6lsb 6lsb 1 0 0 8lsb 8lsb 1 0 1 10lsb 10lsb 1 1 0 12lsb 12lsb 1 1 1 14lsb 14lsb bit 2 ~ bit 0: unimplemented , read as ?0?. 6.7.2 adc data register (addata/rb, addata1h/rc, addata1l/rd) when the ad conversion is completed, the result is loaded to the addata, addata1h and addata1l registers. the adrun bit is cleared, and the adif is set. 6.7.3 adc sampling time the accuracy, linearity, and speed of the successive approximation of ad converter are dependent on the properties of the adc and the comparator. the source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. the application program controls the length of the sample time to meet the specified accuracy. generally speaking, the program should wait for 2 s for each k ? of the analog source impedance and at least 2 s for the low-impedance source. the maximum recommended impedance for analog source is 10k ? at vdd=5v. after the analog input channel is selected, this acquisition time must be done before the conversion is started. 6.7.4 ad conversion time ckr1 and ckr0 select the conversion time (tct), in terms of instruction cycles. this allows the mcu to run at a maximum frequency without sacrificing the ad conversion accuracy. for the em78p342n/343n, the conversion time per bit is 4 s. the table below shows the relationship between tct and the maximum operating frequencies. c kr1: ckr 0 operation mode max. operation frequency max. conversion rate/bit max. conversion rate 00 fsco/16 4 mhz 250khz (4s) 15 4s=60s(16.7khz) 01 fsco/4 1mhz 250khz (4s) 15 4s=60s(16.7khz) 10 fsco/64 16mhz 250khz( 4s) 15 4s=60s(16.7khz) 11 fsco/8 2mhz 250khz (4s) 15 4s=1065s(16.7khz) note pin not used as an analog input pin can be used as a regular input or output pin. during conversion, do not perform output instruction to maintain precision for all of the pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 57 (this specification is subject to change without further notice) 6.7.5 adc operation during sleep mode in order to obtain a more accurate adc value and reduce power consumption, the ad conversion remains operational during sleep mode. as the slep instruction is executed, all the mcu operations will stop except for the oscillator, tcc, tcca, tccb, tccc and ad conversion. the ad conversion is considered completed as determined by : 1. adrun bit of r9 register is cleared to ?0?. 2. adif bit of re register is set to ?1?. 3. adwe bit of the re register is set to ?1.? wake-up from adc conversion (where it remains in operation during sleep mode). 4. wake-up and executes the next instruction if adie bit of ioce0 is enabled and the ?disi? instruction is executed. 5. wake-up and enters into interrupt vector (address 0x00c) if adie bit of ioce0 is enabled and the ?eni? instruction is executed. 6. enters into interrupt vector (address 0x00c) if adie bit of ioce0 is enabled and the ?eni? instruction is executed. the results are fed into the addata, addata1h, and addata1l registers when the conversion is completed. if the adie is enabled, the device will wake up. otherwise, the ad conversion will be shut off, no matter what the status of adpd bit is. 6.7.6 programming process/considerations 6.7.6.1 programming process follow these steps to obtain data from the adc : 1. write to the seven bits (ade7 : ade0) on the r8 (aisr) register to define the characteristics of r5 (digital i/o, analog channels, or voltage reference pin) 2. write to the r9/adcon register to configure the ad module : a) select the adc input channel (adis2 : adis0) b) define the ad conversion clock rate (ckr1 : ckr0) c) select the vrefs input source of the adc d) set the adpd bit to 1 to begin sampling 3. set the adwe bit, if the wake-up function is employed 4. set the adie bit, if the interrupt function is employed 5. write ?eni? instruction, if the interrupt function is employed 6. set the adrun bit to 1 7. write ?slep? instruction or polling. 8. wait for wake-up, adrun bit is cleared to ?0?, interrupt flag (adif) is set ?1,? or adc interrupt occurs. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 58 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 9. read the addata or addata1h and addata1l conversion data registers. if the adc input channel changes at this time, the addata, addata1h, and addata1l values can be cleared to ?0?. 10. clear the interrupt flag bit (adif) 11. for the next conversion, go to step 1 or step 2 as required. at least two tct is required before the next acquisition starts. note in order to obtain accurate values, it is necessary to avoid any data transition on the i/o pins during ad conversion. 6.7.6.2 sample demo programs a. define a general register r_0 == 0 ; indirect addressing register psw == 3 ; status register port5 == 5 port6 == 6 r _ e== 0xe ; interrupt status register b. define a control register ioc50 == 0x5 ; control register of port 5 ioc60 == 0x6 ; control register of port 6 c_int== 0xf ; interrupt control register c. adc control register addata == 0xb ; the contents are the results of adc aisr == 0x08 ; adc input select register adcon == 0x9 ; 7 6 5 4 3 2 1 0 ; vrefs ckr1 ckr0 adrun adpd adis2 adis1 adis0 d. define bits in adcon adrun == 0x4 ; adc is executed as the bit is set adpd == 0x3 ; power mode of adc e. program starts org 0 ; initial address jmp initial ; org 0x0c ; interrupt vector jmp clrre ; ; ; (user program section) ; ; www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 59 (this specification is subject to change without further notice) clrre: mov a,re and a, @0bxx0xxxxx ; to clear the adif bit, ?x? by application mov re,a bs adcon, adrun ; to start to execute the next ad conversion if necessary reti initial: mov a,@0b00000001 ; to define p50 as an analog input mov aisr,a mov a,@0b00001000 ; to select p50 as an analog input channel, and ad power on mov adcon,a ; to define p50 as an input pin and set clock rate at fosc/16 en_adc: mov a, @0bxxxxxxx1 ; to define p50 as an input pin, and the others iow port5 ; are dependent on applications mov a, @0bxxxx1xxx ; enable the adwe wake-up function of adc, ?x? by application mov re,a mov a, @0bxxxx1xxx ; enable the adie interrupt function of adc, ?x? by application iow c_int eni ; enable the interrupt function bs adcon, adrun ; start to run the adc ; if the interrupt function is employed, the following three lines may be ignored ;if sleep: slep ; ; (user program section) ; or ;if polling: polling: jbc adcon, adrun ; to check the adrun bit continuously; jmp polling ; adrun bit will be reset as the ad conversion is completed ; ; (user program section) ; www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 60 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.8 infrared remote control app lication/pwm waveform generation 6.8.1 overview this lsi can easily output infrared carrier or pwm standard waveform. as illustrated below, the ir and pwm waveform generation function include an 8-bit down count timer/counter, high-time, low-time, and ir control register. the irout pin waveform is determined by ioca0 (ir and tccc scale control register), iocb1 (high-time rate, low-time rate control register), ioc81 (t ccc counter), ioca1 (high-time register), and ioc91 (low-time register). h/w modulator 8 hf irout ir fcarrier ft:clk(fosc) lg 8 bit counter 8-to-1 mux 8bit binary down counter auto-reload buffer (tccc)(ioc81) 8 bit counte r 8-to-1 mux 8 bit counter 8-to-1 mux 8bit binary down counter 8bit binary down counter auto-reload buffer (high-time)(ioca1) auto-reload buffer (low-time)(ioc91) 8 8 scale (iocb1) scale (iocb1) scale (ioca0) 8 8 underflow interrupt hpwtif lpwtif fig. 6-12 ir/pwm system block diagram note details of the fcarrier high time width and low time width are explained below : fcarrier = ft/ 2 { [1+decimal tccc counter value (ioc81)] * tccc scale(ioca0) } high time width = { [1+decimal high-time value (ioca1)] * high time scale(iocb1) } / ft low time width = { [1+decimal low-time value (ioc91)] * low time scale(iocb1) } / ft where ft is the system clock ft=fosc/1(clk=2) ft=fosc/2(clk=4) when an interrupt is generated by the high time down counter underflow (when enabled), the next instruction will be fetched from address 018 and 01bh (high time and low time respectively). www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 61 (this specification is subject to change without further notice) 6.8.2 function description the following figure shows lgp=0 and hf=1 . the irout waveform modulates the fcarrier waveform at low-time segments of the pulse. fig. 6-13a lgp=0, hf=1, irout pin output waveform the following figure shows lgp=0 and hf=0 . the irout waveform cannot modulate the fcarrier waveform at low-time segments of the pulse. so irout waveform is determined by the high time width and low time width instead. this mode can produce standard pwm waveform. low time width high time width low time width high time width fcarrier hf irout ire start fig. 6-13b lgp=0, hf=0, irout pin output waveform low time width high time width low time width high time width fcarrier hf irout ire start www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 62 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) the following figure shows lgp=0 and hf=1 . the irout waveform modulates the fcarrier waveform at low-time segments of the pulse. when ire goes low from high, the output waveform of irout will keep transmitting until high-time interrupt occurs. hf low time width high time width low time width high time width fcarrier irout ire ir disable start always high-level fig. 6-13c lgp=0, hf=1, when ire goes low from high, irout pin outputs waveform the following figure shows lgp=0 and hf=0 . the irout waveform cannot modulate the fcarrier waveform at low-time segments of the pulse. so irout waveform is determined by high time width and low time width. this mode can produce standard pwm waveform when ire goes low from high. the output waveform of irout will keep on transmitting until high-time interrupt occurs. low time width high time width low time width high time width fcarrier hf irout ire ir disable start always high-level fig. 6-13d lgp=0, hf=0, when ire goes low from high, irout pin output waveform www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 63 (this specification is subject to change without further notice) the following figure shows lgp=1 and hf=1 . when this bit is set to high level, the high-time segment of the pulse is ignored. so, irout waveform output is determined by low-time width. low time width low time width low time width fcarrier hf irout ire ir disable start always high-level fig. 6-13e lgp=1 and hp=1, irout pin output waveform 6.8.3 programming the related registers when defining ir/pwm, refer to the operation of the related registers as shown in the tables below. ir/pwm related control registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x09 ioc90 tccbhe/0tccben/0 tccbts/0 tccbte/0 0 t cccen/0tcccts/0 tcccte / 0 0x0a ir cr /ioca0 tcccse/0 tcccs2/0 tcccs1/0 tcccs0/0 ire/0 hf/0 lgp/0 iroute/0 0x0f imr /iocf0 lpwtie/0 hpwtie/0 tcccie/0 tccbie/0 tccaie/0 exie/0 icie/0 tcie/0 0x0b hlts /iocb1 htse/0 hts2/0 hts1/0 hts0/0 ltse/0 lts2/0 lts1/0 lts0/0 ir/pwm related status/data registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0f isr/rf lpwtif/0 hpwtif/0 tcccif/0 tccbif/0 tccaif/0 exif/0 icif/0 tcif/0 0x06 tccc /ioc81 tccc7/0 tccc6/0 tccc5/0 tccc4/0 tccc3/0 tccc2/0 tccc1/0 tccc0/0 0x09 ltr /ioc91 ltr7/0 ltr6/0 ltr5/0 ltr4/0 ltr3/0 ltr2/0 ltr1/0 ltr0/0 0x0a htr /ioca1 htr7/0 htr6/0 htr5/0 htr4/0 htr3/0 htr2/0 htr1/0 htr0/0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 64 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.9 timer/counter 6.9.1 overview timer a (tcca) is an 8-bit clock counter. timer b (tccb) is a 16-bit clock counter. timer c (tccc) is an 8-bit clock counter t hat can be extended to 16-bit clock counter with programmable scalers. tcca, tccb , and tccc can be read and written to, and are cleared at every reset condition. 6.9.2 function description set predict value system clock or external input external input tccc set tcccif tcccen overflow tcca set tccaif tccaen overflow tccb set tccbif tccben overflow set predict value set predict value external input 8-to-1 mux 8 bit counter system clock or system clock or tcccs1 ~ tcccs0 fig. 6.14 timer block diagram each signal and block of the above timer block diagram is described as follows: tccx: timer a~c register. tccx is incremented until it matches with zero, and then reloads the predicted value. when writing a value to tccx, the predicted value and tccx value become the set value. when reading from tccx, the value will be the tccx direct value. when tccxen is enabled, the reloading of the predicted value to tccx, tccxie is also enabled. tccxif will be set at the same time. it is an up counter. tcca counter (ioc51): ioc51 (tcca) is an 8-bit clock counter. it can be read, written to, and cleared on any reset condition and is an up counter. note tcca timeout period [1/fosc x (256-tcca cnt) x 1 (clk=2)] tcca timeout period [1/fosc x (256-tcca cnt) x 2 (clk=4)] tccb counter (ioc61): ioc61 is an 8-bit clock counter for the least significant byte of tccbx (tccb). it can be read, written, and cleared on any reset condition and is an up counter. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 65 (this specification is subject to change without further notice) tccbh / msb counter (ioc71): ioc71 is an 8-bit clock counter for the most significant byte of tccbx (tccbh). it can be read, written to, and cleared on any reset condition. when tccbhe (ioc90) is ?0,? then tccbh is disabled. when tccbhe is?1,? then tccb is a 16-bit length counter. note when tccbh is disabled: tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 1 (clk=2)] tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 2 (clk=4)] when tccbh is enabled: tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 1 (clk=2)} tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 2 (clk=4)} tccc counter (ioc81): ioc81 (tccc) is an 8-bit clock counter. it can be read, written to, and cleared on any reset condition. if hf (bit 2 of ioca0) = 1 and ire (bit 3 of ioca0) = 1, tccc counter scale uses the low-time segments of the pulse generated by fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). the tccc value will then be the tccc predicted value. when hp = 0 or ire = 0. the tccc is an up counter. note in tccc up counter mode: tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 1(clk=2)] tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 2(clk=4)] when hp = 1 and ire = 1, the tccc counter scale uses the low-time segments of the pulse generated by the fcarrier frequency modulation. note in ir mode: fcarrier = ft/ 2 { [1+decimal tccc counter value (ioc81)] x tccc scale (ioca0) } ft is system clock: ft = fosc/1 (clk=2) ft = fosc/2 (clk=4) www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 66 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.9.3 programming the related registers when defining tccx, refer to the operation of its related registers as shown in the tables below. tccx related control registers : address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x08 ioc80 0 0 cpout/0 cos1/0 cos0/0 tccaen /0 tccats /0 tccate /0 0x09 ioc90 tccbhe /0 tccben /0 tccbts /0 tccbte /0 0 tcccen /0 tcccts /0 tcccte /0 0x0a ir cr /ioca0 tcccse /0 tcccs2 /0 tcccs1/ 0 tcccs0 /0 ire/0 hf/0 lgp/0 iroute/0 0x0f imr /iocf0 lpwte/0 hpwte/0 tcccie/0 tccbie/0 tccaie/0 exie/0 icie/0 tcie/0 related tccx status/data registers : address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0f isr/rf lpwtf/0 hpwtf/0 tcccif/0 tccbif/0 tccaif/0 exif/0 icif/0 tcif/0 0x05 tcca /ioc51 tcca7/0 tcca6/0 tcca5/0 tcca4/0 tcca3/0 tcca2/0 tcca1/0 tcca0/0 0x06 tccb /ioc61 tccb7/0 tccb6/0 tccb5/0 tccb4/0 tccb3/0 tccb2/0 tccb1/0 tccb0/0 0x07 tccbh /ioc71 tccbh7 /0 tccbh6 /0 tccbh5 /0 tccbh4 /0 tccbh3 /0 tccbh2 /0 tccbh1 /0 tccbh0 /0 0x08 tccc /ioc81 tccc7/0 tccc6/0 tccc5/0 tccc4/0 tccc3/0 tccc2/0 tccc1/0 tccc0/0 6.10 comparator the em78p342n/343n has one comparator which has two analog inputs and one output. the comparator can be employed to wake up the system from sleep mode. the figure at right shows the comparator circuit. cin - - + cmp cin+ co cin+ cin - output 10mv fig. 6.15 comparator operating mode www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 67 (this specification is subject to change without further notice) 6.10.1 external reference signal the analog signal that is presented at cin ? is compared to the signal at cin+. the digital output (co) of the comparator is adjusted accordingly by taking into consideration the following notes: note the reference signal must be between vss and vdd. the reference voltage can be applied to either pin of the comparator. threshold detector applications may be of the same reference. the comparator can operate from the same or different reference sources. 6.10.2 comparator outputs ? the compared result is stored in the cmpout of ioc80. ? the comparator outputs are sent to co (p64) by programming bit 4 & bit 3 of the ioc80 register to <1,0>. see table under section 6.2.4, ioc80 (comparator and tcca control registers) for comparator/op select bits function description . the following figure shows the comparator output block diagram. q q en en d d to c0 to cpif to cmpout cmrd cmrd from other comparator reset from op i/o fig. 6-16 comparator output configuration www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 68 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.10.3 using a comparator as an operation amplifier the comparator can be used as an operation amplifier if a feedback resistor is externally connected from the input to the output. in this case, the schmitt trigger can be disabled for power saving purposes, by setting bit 4, bit 3 of the ioc80 register to <1,1>. see table under section 6.2.4, ioc80 (comparator and tcca control registers) for comparator/op select bits function description . note under operation amplifier: the cmpie (ioce0.4), cmpwe (re.2), and cmpif (re.4) bits are invalid. the comparator interrupt is invalid. the comparator wake-up is invalid. 6.10.4 comparator interrupt ? cmpie (ioce0.4) must be enabled for the ?eni? instruction to take effect ? interrupt is triggered whenever a change occurs on the comparator output pin ? the actual change on the pin can be determined by reading the bit cmpout, ioc80<5>. ? cmpif (re.4), the comparator interrupt flag, can only be cleared by software 6.10.5 wake-up from sleep mode ? if the cmpwe bit of the re register is set to ?1,? the comparator remains active and the interrupt remains functional, even under sleep mode. ? if a mismatch occurs, the change will wake up the device from sleep mode. ? the power consumption should be taken into consideration for the benefit of energy conservation. ? if the function is unemployed during sleep mode, turn off the comparator before entering into sleep mode. the comparator is considered completed as determined by : 1. cos1 and cos0 bits of ioc80 register setting selects comparator. 2. cmpif bit of re register is set to ?1?. 3. cmpwe bit of re register is set to ?1?. wakes-up from comparator (where it remains in operation during sleep mode) 4. wakes-up and executes the next instruction, if cmpie bit of ioce0 is enabled and the ?disi? instruction is executed. 5. wake-up and enters into interrupt vector (address 0x00f), if adie bit of ioce0 is enabled and the ?eni? instruction is executed 6. enters into interrupt vector (address 0x00f), if cmpie bit of ioce0 is enabled and the ?eni? instruction is executed. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 69 (this specification is subject to change without further notice) 6.11 oscillator 6.11.1 oscillator modes the EM78P341N/342n/343n can be operated in six different oscillator modes, such as high crystal oscillator mode 1 (hxt1), high crystal oscillator mode 2 (hxt2), low crystal oscillator mode 1 (lxt1), low crystal oscillator mode 2 (lxt2), external rc oscillator mode (erc), and rc oscillator mode with internal rc oscillator mode (irc). you can select one of them by programming the osc2, ocs1, and osc0 in the code option register. the oscillator modes defined by osc2, ocs1, and osc0 are described below. oscillator modes osc2 osc1 osc0 erc 1 (external rc oscillator mode); p70/osco acts as p70 0 0 0 erc 1 (external rc oscillator mode); p70/osco acts as osco 0 0 1 irc 2 (internal rc oscillator mode); p70/osco acts as p70 0 1 0 irc 2 (internal rc oscillator mode); p70/osco acts as osco 0 1 1 lxt1 3 (frequency range of xt mode is 1mhz ~ 100khz) 1 0 0 hxt1 3 (frequency range of xt mode is 20mhz ~ 6mhz) 1 0 1 lxt2 3 (frequency range of xt mode is 32khz) 1 1 0 hxt2 3 (frequency range of xt mode is 6mhz ~ 1mhz) (default) 1 1 1 1 in erc mode, osci is used as osc illator pin. osco /p50 is defined by code option word 0 bit 6 ~ bit 4. 2 in irc mode, p55 is normal i/o pin. osco/p70 is defined by code option word 0 bit 6 ~ bit 4. 3 in lxt1, lxt2, hxt1 and hxt2 modes; osci and osco are used as osc illator pins. thes e pins cannot and should not be defined as normal i/o pins. the maximum operating frequency limit of crystal/resonator at different vdds, are as follows : conditions vdd max. freq. (mhz) 1.7 4 3.0 16 two clocks 4.0 20 6.11.2 crystal oscillator/ceramic resonators (crystal) the EM78P341N/342n/343n can be driven by an external clock signal through the osci pin as illustrated below. osci osco fig. 6-17 external clock input circuit www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 70 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) in most applications, pin osci and pin osco can be connected with a crystal or ceramic resonator to generate oscillation. fig. 6-18 below depicts such a circuit. the same applies to the hxt1 mode, htx2 mode, lxt1 mode and lxt2 mode. osci osco crystal rs c2 c1 fig. 6-18 crystal/resonator circuit the following table provides the recommended values for c1 and c2. since each resonator has its own attribute, user should refer to the resonator specifications for the appropriate values of c1 and c2. rs, a serial resistor, may be required for at strip cut crystal or low frequency mode. capacitor selection guide for crystal oscillator or ceramic resonators : oscillator type frequency mode frequency c1 (pf) c2 (pf) 455khz 100~150 100~150 2.0 mhz 20~40 20~40 ceramic resonators hxt 4.0 mhz 10~30 10~30 32.768khz 25 15 100khz 25 25 lxt 200khz 25 25 455khz 20~40 20~150 1.0 mhz 15~30 15~30 2.0 mhz 15 15 crystal oscillator hxt 4.0 mhz 15 15 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 71 (this specification is subject to change without further notice) circuit diagrams for serial and parallel modes crystal/resonator : osci c 7404 330 330 crysta l 7404 7404 fig. 6-19 serial mode crystal/resonator circuit diagram osci 7404 7404 c1 c2 10k 4.7k vdd 10k 10k crystal fig. 6-20 parallel mode crystal/resonator circuit diagram 6.11.3 external rc oscillator mode for some applications that do not require precise timing calculation, the rc oscillator (fig. 6-21 at right) offers a cost- effective solution. nevertheless, it should be noted that the frequency of the rc oscillator is influenced by the supply voltage, the values of the resistor (rext), the capacitor (cext), and even by the operation temperature. moreover, the frequency also changes slightly from one chip to another due to manufacturing process variations. osci vcc rext cext fig. 6-21 external rc oscillator mode circuit in order to maintain a stable system frequency, the values of the cext should be no less than 20pf, and that of rext should be no greater than 1m ? . if the frequency cannot be kept within this range, the frequency can be affected easily by noise, humidity, and leakage. the smaller the rext in the rc oscillator is, the faster its frequency will be. on the contrary, for very low rext values, for instance, 1 k ? , the oscillator will become unstable because the nmos cannot correctly discharge the capacitance current. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 72 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the rc oscillator, the package types, and the pcb layout have certain effects on the system frequency. the rc oscillator frequencies : cext rext average fosc 5v, 25 c average fosc 3v, 25 c 3.3k 3.5 mhz 3.2 mhz 5.1k 2.5 mhz 2.3 mhz 10k 1.30 mhz 1.25 mhz 20 pf 100k 140 khz 140khz 3.3k 1.27 mhz 1.21 mhz 5.1k 850khz 820khz 10k 450khz 450khz 100 pf 100k 48khz 50khz 3.3k 560khz 540khz 5.1k 370khz 360khz 10k 196khz 192khz 300 pf 100k 20khz 20khz note: 1 : measured based on dip packages. 2 : the values are for design reference only. 3 : the frequency drift is 30% 6.11.4 internal rc oscillator mode the EM78P341N/342n/343n offers a versatile internal rc mode with default frequency value of 4mhz. internal rc oscillator mode has other frequencies (1mhz, 8mhz, and 455khz) that can be set by code option (word 1), rcm1, and rcm0. the table below describes the EM78P341N/342n/343n internal rc drift with voltage, temperature, and process variations. internal rc drift rate (ta=25c, vdd=5v ? 5%, vss=0v) drift rate internal rc frequency temperature (-40 c ~+85 c ) voltage (2.3v~5.5v) process total 4mhz 5% 5% 4% 14% 16mhz 5% 5% 4% 14% 1mhz 5% 5% 4% 14% 455mhz 5% 5% 4% 14% theoretical values are for reference only. actual values may vary depending on the actual process. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 73 (this specification is subject to change without further notice) 6.12 power-on considerations any microcontroller is not warranted to start operating properly before the power supply stabilizes in steady state. the EM78P341N/342n/343n por voltage range is 1.55 ~ 1.7v. under customer application, when power is switched off, vdd must drop below 1.9v and remains at off state for 10 s before power can be switched on again. subsequently, the EM78P341N/342n/343n will reset and work normally. the extra external reset circuit will work well if vdd rises fast enough (50ms or less). however, under critical applications, extra devices are still required to assist in solving power-on problems. 6.12.1 programmable wdt time-out period the option word (wdtps) is used to define the wdt time-out period (18ms 5 or 4.5ms 6 ). theoretically, the range is from 4.5ms or 18ms. for most crystal or ceramic resonators, the lower the operation frequency is, the longer is the required set-up time. 6.12.2 external power-on reset circuit the circuit shown in the following figure implements an external rc to produce a reset pulse. the pulse width (time constant) should be kept long enough to allow the vdd to reach the minimum operating voltage. this circuit is used when the power supply has a slow power rise time. because the current leakage from the /reset pin is about 5 a, it is recommended that r should not be greater than 40 k. this way, the voltage at pin /reset is held below 0.2v. the diode (d) functions as a short circuit at power-down. the ?c? capacitor is discharged rapidly and fully. rin, the current-limited resistor, prevents high current discharge or esd (electrostatic discharge) from flowing into pin /reset. /reset vdd d r rin c fig. 6-22 external power-on reset circuit 5 vdd=5v, wdt time-out period = 16.5ms 30%. vdd=3v, wdt time-out period = 18ms 30%. 6 vdd=5v, wdt time-out period = 4.2ms 30%. vdd=3v, wdt time-out period = 4.5ms 30%. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 74 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.12.3 residual voltage protection when the battery is replaced, device power (vdd) is removed but the residual voltage remains. the residual voltage may trip below vdd minimum, but not to zero. this condition may cause a poor power-on reset. fig. 6-23 and fig. 6-24 show how to create a protection circuit against residual voltage. /reset vdd 100k q1 1n4684 10k 33k vdd fig. 6-23 residual voltage protection circuit 1 /reset vdd q1 vdd r3 r2 r1 fig. 6-24 residual voltage protection circuit 2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 75 (this specification is subject to change without further notice) 6.13 code option EM78P341N/342n/343n has two code option words and one customer id word that are not part of the normal program memory. word 0 word1 word 2 bit 12 ~ bit 0 bit 12 ~ bit 0 bit12 ~ bit 0 6.13.1 code option register (word 0) word 0 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lvr1 lvr0 type1 type0 clks enwdtb osc2 osc1 osc0 hlp ? ? ? bits 12~11 (lvr1 ~ lvr0): low voltage reset enable bits lvr1, lvr0 vdd reset level vdd release level 11 na (power-on reset) (default) 10 2.7v 2.9v 01 3.5v 3.7v 00 4.0v 4.2v bits 10~9 (type1 ~ type0): type selection for em78p343n or em78p342n or EM78P341N or 108c. type 1, type 0 vdd reset level 00 108c (8-pin) 01 EM78P341N (14-pin) 10 em78p342n (18-pin) 11 em78p343n (default) (20-pin) bit 8 (clks): instruction period option bit 0 = two oscillator periods 1 = four oscillator periods (default) refer to section 6.15 for instruction set bit 7 (enwdtb): watchdog timer enable bit 0 = enable 1 = disable (default) www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 76 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) bits 6, 5 & 4 (osc2, osc1 & osc0): oscillator modes selection bits oscillator modes osc2 osc1 osc0 erc 1 (external rc oscillator mode); p70/osco acts as p70 0 0 0 erc 1 (external rc oscillator mode); p70/osco acts as osco 0 0 1 irc 2 (internal rc oscillator mode); p70/osco acts as p70 0 1 0 irc 2 (internal rc oscillator mode); p70/osco acts as osco 0 1 1 lxt1 3 (frequency range of xt mode is 1mhz ~ 100khz) 1 0 0 hxt1 3 (frequency range of xt mode is 20mhz ~ 6mhz) 1 0 1 lxt2 3 (frequency range of xt mode is 32khz) 1 1 0 hxt2 3 (frequency range of xt mode is 6mhz ~ 1mhz) (default) 1 1 1 1 in erc mode, osci is used as osc illator pin. osco /p70 is defined by code option word 0 bit 6 ~ bit 4. 2 in irc mode, p55 is normal i/o pin. osco/p70 is defined by code option word 0 bit 6 ~ bit 4. 3 in lxt1, lxt2, hxt1 and hxt2 modes; osci and osco are used as osc illator pins. thes e pins cannot and should not be defined as normal i/o pins. bit 3 (hlp): power consumption selection 0 = low power consumption, applies to working frequency at 4mhz or below 4mhz 1 = high power consumption, applies to working frequency above 4mhz (default) bits 2 ~ 0: not used (reserved) 6.13.2 code option register (word 1) word 1 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? jmpts rcout nrhl nre cyes c3 c2 c1 c0 rcm1 rcm0 bits 12~11: not used, (reserved). these bits are set to ?1? all the time. bit 10 (jmpts): long instruction enable 0 = disable lcall, ljmp instruction 1 = enable lcall, ljmp instruction.(default) bit 8 (rcout): system clock output enable bit in irc or erc mode 0 = osco pin is open drain 1 = osco output system clock (default) bit 8 (nrhl): noise rejection high/low pulses define bit. int pin is falling or rising edge trigger 0 = pulses equal to 8/fc is regarded as signal 1 = pulses equal to 32/fc is regarded as signal (default) note the noise rejection function is turned off under the lxt and sleep mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 77 (this specification is subject to change without further notice) bit 7 (nre): noise rejection enable 0 = disable noise rejection 1 = enable noise rejection (default), but in low crystal oscillator (lxt) mode, the noise rejection circuit is always disabled. bit 6 (cyes): instruction cycle selection bit 0 = one instruction cycle 1 = two instructions cycles (default) bit 5, 4, 3, & bit 2 (c3, c2, c1, c0 ) : calibrator of internal rc mode c3, c2, c1, & c0 must be set to ?1? only (auto-calibration). bit 1 & bit 0 (rcm1, rcm0): rc mode selection bits rcm 1 rcm 0 frequency (mhz) 1 1 4(default) 1 0 16 0 1 1 0 0 455khz 6.13.3 customer id register (word 2) word 2 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? resetenb ? wdtps bits 12 ~ 9: not used (reserved). these bits are set to ?1? all the time. bit 8 (resetenb): p71/reset pin select bit 1 = p71 is general purpose input pin or open-drain for output port (default) 0 = p71 set to /reset pin bit 7: not used (reserved). this bit is set to ?1? all the time. bit 6 (wdtps): wdt time-out period selection bit wdt time watchdog timer * 1 18 ms (default) 0 4.5 ms * theoretical values, for reference only bits 5 ~ 0: customer?s id code www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 78 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.14 low voltage detector during a power source unstable situation, like external power noise interference or ems test condition, will cause the power to vibrate fiercely. at the time the vdd is unsettled, it maybe below working voltage. when the system supply voltage vdd is below the working voltage, the ic kernel must keep all register status automatically. 6.14.1 low voltage reset lvr property is setting at code option word 0, bit 10,9 detail operation mode as following : word 0 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lvr1 lvr0 type1 type0 clks enwdtb osc2 osc1 osc0 hlp ? ? ? bits 12~11 (lvr1 ~ lvr0): low voltage reset enable bits. lvr1, lvr0 vdd reset level vdd release level 11 na (power-on reset) 10 2.7v 2.9v 01 3.5v 3.7v 00 4.0v 4.2v 6.14.2 low voltage detector lvd property is setting at register detail operation mode as following: 6.14.2.1 iocd1 (lvd control register) bit 7 6 5 4 3 2 1 0 em78p342l/343l - - - - lvdie lvden lvd1 lvd0 ice342n type1 type0 lvr1 lvr0 lvdie lvden lvd1 lvd0 note iocd1< 3 > register is both readable and writable individual interrupt is enabled by setting its associated control bit in the iocd1< 4 > to "1." global interrupt is enabled by the eni instruction and is disabled by the disi instruction. refer to fig. 6-8 (interrupt input circuit) under section 6.6 (interrupt). bit 3 (lvdie): low voltage detector interrupt enable bit. 0 = disable low voltage detector interrupt 1 = enable low voltage detector interrupt when the detect low level voltage state is used to enter an interrupt vector or enter next instruction, the lvdie bit must be set to ?enable?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 79 (this specification is subject to change without further notice) bit 2 (lvden): low voltage detector enable bit 0 = low voltage detector disable 1 = low voltage detector enable bits 1~0 (lvd1:0): low voltage detector level bits. lvden lvd1, lvd0 lvd voltage interrupt level /lvd vdd 2.3v 0 1 11 vdd > 2.3v 1 vdd 3.3v 0 1 10 vdd > 3.3v 1 vdd 4.0v 0 1 01 vdd > 4.0v 1 vdd 4.5v 0 1 00 vdd > 4.5v 1 0 na 0 6.14.2.2 re (interrupt status 2 & wake-up control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 /lvd lvdif adif cmpif adwe cmpwe icwe lvdwe note re < 6, 5, 4 > can be cleared by instruction but cannot be set. ioce0 is the interrupt mask register. reading re will result to "logic and" of re and ioce0. bit 7 (/lvd): low voltage detector state. this is a read only bit. when the vdd pin voltage is lower than lvd voltage interrupt level (selected by lvd1 and lvd0), this bit will be cleared. 0 = low voltage is detected. 1 = low voltage is not detected or lvd function is disabled. bit 6 (lvdif): low voltage detector interrupt flag lvdif reset to ?0? by software or hardware. bit 0 (lvdwe): low voltage detect wake-up enable bit. 0 = disable low voltage detect wake-up. 1 = enable low voltage detect wake-up. when the low voltage detect is used to enter an interrupt vector or to wake up the ic from sleep with low voltage detect running, the lvdwe bit must be set to ?enable?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 80 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 6.14.3 programming process follow these steps to obtain data from the lvd : 1. write to the two bits (lvd1: lvd0) on the lvdcr register to define the lvd level. 2. set the lvdwe bit, if the wake-up function is employed. 3. set the lvdie bit, if the interrupt function is employed. 4. write ?eni? instruction, if the interrupt function is employed. 5. set lvden bit to 1 6. write ?slep? instruction or polling /lvd bit. 7. clear the interrupt flag bit (lvdif) when low voltage detector interrupt occurred. the internal lvd module uses the internal circuit, and when the code option is set to enable the lvd module, the current consumption will increase to about 5a. during sleep mode, the lvd module continues to operate. if the device voltage drops slowly and crosses the detect point, the lvdif bit will be set and the device will wake up from sleep mode. the lvd interrupt flag is still set as the prior status. when the system resets, the lvd flag will be cleared. figure 6-25 shows the lvd module to detect the external voltage situation. when vdd drops not below vlvd, lvdif is kept at ?0?. when vdd drops below vlvd, lvdif is set to ?1?. if global eni is enabled, lvdif will be set to ?1?, the next instruction will branch to an interrupt vector. the lvd interrupt flag is cleared to ?0? by software. when vdds drops below vreset and it is less than 80s, the system will keep all the register status and the system halts but oscillation is active. when vdd drops below vreset and it is more than 80s, a system reset will occur. refer to section 6.5.1 for detailed reset description. vdd lvdif internal reset v lvd v reset lvdif is cleared by software vdd < vreset not longer than 80us, the system still keeps on operating lvr voltage drop fig. 6-25 lvd waveform situation www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 81 (this specification is subject to change without further notice) 6.15 instruction set each instruction in the instruction set is a 13-bit word divided into an op code and one or more operands. normally, all instructions are executed within one single instruction cycle (one instruction consists of two oscillator periods), unless the program counter is changed by instructions "mov r2,a," "add r2,a," or by instructions of arithmetic or logic operation on r2 (e.g., "sub r2,a," "bs(c) r2,6," "clr r2," etc.). in this case, these instructions need one or two instruction cycles as determined by the code option register cyes bit. in addition, the instruction set has the following features : 1. every bit of any register can be set, cleared, or tested directly. 2. the i/o registers can be regarded as general registers. that is, the same instruction can operate on i/o registers. the following symbols are used in the instruction set table : convention: r = register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. b = bit field designator that selects the value for the bit located in the register r and which affects the operation. k = 8 or 10-bit constant or literal value binary instruction hex mnemonic operation status affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a cont none 0 0000 0000 0011 0003 slep 0 wdt, stop oscillator t, p 0 0000 0000 0100 0004 wdtc 0 wdt t, p 0 0000 0000 rrrr 000r iow r a iocr none 1 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 ret [top of stack] pc none 0 0000 0001 0011 0013 reti [top of stack] pc, enable interrupt none 0 0000 0001 0100 0014 contr cont a none 0 0000 0001 rrrr 001r ior r iocr a none 1 0 0000 01rr rrrr 00rr mov r,a a r none 0 0000 1000 0000 0080 clra 0 a z 0 0000 11rr rrrr 00rr clr r 0 r z 0 0001 00rr rrrr 01rr sub a,r r-a a z, c, dc 0 0001 01rr rrrr 01rr sub r,a r-a r z, c, dc 0 0001 10rr rrrr 01rr deca r r-1 a z 0 0001 11rr rrrr 01rr dec r r-1 r z 0 0010 00rr rrrr 02rr or a,r a vr a z 0 0010 01rr rrrr 02rr or r,a a vr r z www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 82 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) binary instruction hex mnemonic operation status affected 0 0010 10rr rrrr 02rr and a,r a & r a z 0 0010 11rr rrrr 02rr and r,a a & r r z 0 0011 00rr rrrr 03rr xor a,r a r a z 0 0011 01rr rrrr 03rr xor r,a a r r z 0 0011 10rr rrrr 03rr add a,r a + r a z, c, dc 0 0011 11rr rrrr 03rr add r,a a + r r z, c, dc 0 0100 00rr rrrr 04rr mov a,r r a z 0 0100 01rr rrrr 04rr mov r,r r r z 0 0100 10rr rrrr 04rr coma r /r a z 0 0100 11rr rrrr 04rr com r /r r z 0 0101 00rr rrrr 05rr inca r r+1 a z 0 0101 01rr rrrr 05rr inc r r+1 r z 0 0101 10rr rrrr 05rr djza r r-1 a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) a(n-1), r(0) c, c a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) r(n-1), r(0) c, c r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) a(n+1), r(7) c, c a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) r(n+1), r(7) c, c r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) a(4-7), r(4-7) a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 r(b) none 2 0 101b bbrr rrrr 0xxx bs r,b 1 r(b) none 3 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip n one 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip n one 1 00kk kkkk kkkk 1kkk call k pc+1 [sp], (page, k) pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) pc none 1 1000 kkkk kkkk 18kk mov a,k k a none 1 1001 kkkk kkkk 19kk or a,k a k a z 1 1010 kkkk kkkk 1akk and a,k a & k a z 1 1011 kkkk kkkk 1bkk xor a,k a k a z 1 1100 kkkk kkkk 1ckk retl k k a, [top of stack] pc none 1 1101 kkkk kkkk 1dkk sub a,k k-a a z, c, dc 1 1110 1000 kkkk k kkkk kkkk kkkk 1eak lcall k pc+1 [sp], k pc none 1 1110 1000 kkkk k kkkk kkkk kkkk 1ebk ljmp k k pc none 1 1111 kkkk kkkk 1fkk add a,k k+a a z, c, dc note: 1 this instruction is applicable to ioc50~iocf0, ioc51 ~ iocf1 only. 2 this instruction is not recommended for rf operation. 3 this instruction cannot operate under rf. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 83 (this specification is subject to change without further notice) 7 absolute maximum ratings items rating temperature under bias -40 c to 85 c storage temperature -65 c to 150 c input voltage vss-0.3v to vdd+0.5v output voltage vss-0.3v to vdd+0.5v working voltage 2.5v to 5.5v working frequency dc to 20mhz 8 dc electrical characteristics ta=25 c, vdd=5.0v 5%, vss=0v symbol parameter condition min typ max unit crystal: vdd to 5v dc ? 20 mhz crystal: vdd to 3v two cycles with two clocks dc ? 8 mhz erc: vdd to 5v r: 5.1k ? , c: 100 pf f 30 % 830 f 30 % khz fxt irc: vdd to 5 v 8mhz,4mhz, 1mhz, 455khz f 30 % f f 30 % hz irc1 irc:vdd to 5v rcm0:rcm1=1:1 3.84 4.0 4.16 mhz irc2 irc:vdd to 5v rcm0:rcm1=1:0 7.68 8.0 8.32 mhz irc3 irc:vdd to 5v rcm0:rcm1=0:1 0.96 1.0 1.06 mhz irc4 irc:vdd to 5v rcm0:rcm1=0:0 436.8 455 473.2 khz vihrc input high threshold voltage (schmitt trigger ) osci in rc mode ? 3.5 ? v vilrc input low threshold voltage (schmitt trigger ) osci in rc mode ? 1.5 ? v iil input leakage current for input pins vin = vdd, vss -1 0 1 a vih1 input high voltage (schmitt trigger ) ports 5, 6, 7 ? 3.75 ? v vil1 input low voltage (schmitt trigger ) ports 5, 6, 7 ? 1.25 ? v viht1 input high threshold voltage (schmitt trigger ) /reset ? 2.0 ? v vilt1 input low threshold voltage (schmitt trigger ) /reset ? 1.0 ? v viht2 input high threshold voltage (schmitt trigger ) tcc, int ? 3.75 ? v vilt2 input low threshold voltage (schmitt trigger ) tcc, int ? 1.25 ? v vihx1 clock input high voltage osci in crystal mode ? 3.5 ? v vilx1 clock input low voltage osci in crystal mode ? 1.5 ? v ioh1 output high voltage (ports 5, p60~66,p70) voh = vdd-0.5v ? -3.7 ? ma ioh2 output high voltage (ir out (port 67)) voh = vdd-0.5v ? -10 ? ma www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 84 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) symbol parameter condition min typ max unit iol1 output low voltage (ports 5, p60~66, p70) vol = gnd+0.5v ? 10 ? ma iol2 output low voltage (ir out (port 67)) vol = gnd+0.5v ? 15 ? ma iph pull-high current pull-high active, input pin at vss -70 -75 -80 a ipl pull-low current pull-low active, input pin at vdd 35 40 45 a isb1 power down current all input and i/o pins at vdd, output pin floating, wdt disabled ? 1.0 2.0 a isb2 power down current all input and i/o pins at vdd, output pin floating, wdt enabled ? 6.0 10 a icc1 operating supply current at two clocks (vdd to 3v) /reset= 'high', fosc=32khz (crystal type,clks="0"), output pin floating, wdt disabled ? 15 20 a icc2 operating supply current at two clocks (vdd to 3v) /reset= 'high', fosc=32khz (crystal type,clks="0"), output pin floating, wdt enabled ? 15 25 a icc3 operating supply current at two clocks /reset= 'high', fosc=4mhz (crystal type, clks="0"), output pin floating, wdt enabled ? 1.9 2.2 ma icc4 operating supply current at two clocks /reset= 'high', fosc=10mhz (crystal type, clks="0"), output pin floating, wdt enabled ? 3.0 3.5 ma note: 1. these parameters are hypothetical (not tested) and are provided for design reference use only. 2. data under minimum, typical, & maximum (min, typ, & max) columns are based on hypothetical results at 25 c. these data are for design reference only. 8.1 ad converter characteristics vdd=2.5v to 5.5v, vss=0v, ta=25 c symbol parameter condition min. typ. max. unit v aref 2.5 ? vdd v v ass analog reference voltage v aref - v ass 2.5v vss ? vss v vai analog input voltage ? v ass ? v aref v ivdd 750 850 1000 ua iai1 ivref analog supply current vdd=v aref =5.0v, v ass =0.0v (v referenced from vdd) ?10 0 +10 ua ivdd 500 600 820 ua iai2 ivref analog supply current vdd=v aref =5.0v, v ass =0.0v (v referenced from vref) 200 250 300 ua iop op current vdd=5.0v, op used output voltage swing 0.2v to 4.8v 450 550 650 ua rn resolution vdd=v aref =5.0v, v ass =0.0v 10 11 ? bits ln linearity error vdd = 2.5 to 5.5v ta=25 c 0 4 8 lsb dnl differential nonlinear error vdd = 2.5 to 5.5v ta=25 c 0 0.5 0.9 lsb fse full scale error vdd=v aref =5.0v, v ass =0.0v 0 4 8 lsb www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 85 (this specification is subject to change without further notice) symbol parameter condition min. typ. max. unit oe offset error vdd=v aref =5.0v, v ass =0.0v 0 2 4 lsb zai recommended impedance of analog voltage source ? 0 8 10 k ? tad adc clock period vdd=v aref =5.0v, v ass =0.0v 4 ? ? us tcn ad conversion time vdd=v aref =5.0v, v ass =0.0v 15 ? 15 tad adiv adc op input voltage range vdd=v aref =5.0v, v ass =0.0v 0 ? v aref v 0 0.2 0.3 adov adc op output voltage swing vdd=v aref =5.0v, v ass =0.0v, rl=10k ? 4.7 4.8 5 v adsr adc op slew rate vdd=v aref =5.0v, v ass =0.0v 0.1 0.3 ? v/us psr power supply rejection vdd=5.0v0.5v 0 ? 2 lsb note: 1. these parameters are hypothetical (not tested) and are provided for design reference use only. 2. there is no current consumption when adc is off other than minor leakage current. 3. ad conversion resu lt will not decr ease when an increase of input volt age and no missing code will result. 4. these parameters are subject to change without further notice. 8.2 comparator (o p) characteristics vdd = 5.0v, vss=0v, ta=25 c symbol parameter condition min. typ. max. unit sr slew rate 0.1 0.2 v/us ivr input voltage range vdd =5.0v, v ss =0.0v 0 5 v 0 0.2 0.3 ovs output voltage swing vd =5.0v, v ss =0.0v, rl=10k ? 4.7 4.8 5 v iop supply current of op 250 350 500 ua ico supply current of comparator 300 ua psr r power-supply rejection ration for op vdd= 5.0v, v ss =0.0v 50 60 70 db vs operating range 2.5 5.5 v note: 1. these parameters are hypothetical (not tested) and are provided for design reference use only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 86 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 8.3 device characteristics the graphs below were derived based on a limited number of samples and they are provided for reference only. hence, the device characteristic shown herein cannot be guaranteed as fully accurate. in these graphs, the data may be out of the specified operating warranted range. irc osc frequency (vdd=3v) temperature o c frequency (mhz) . fig. 8-1 internal rc osc frequency vs. temperature, vdd=3v irc osc frequency (vdd=5v) temperature (
) frequency (m hz) . fig. 8-2 internal rc osc frequency vs. temperature, vdd=5v www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 87 (this specification is subject to change without further notice) 9 ac electrical characteristic ta=-40 to 85 c, vdd=5v 5%, vss=0v symbol parameter conditions min type max unit dclk input clk duty cycle ? 45 50 55 % crystal type 100 ? dc ns tins instruction cycle time (clks="0") rc type 500 ? dc ns ttcc tcc input time period ? (tins+20)/n * ? ? ns tdrh device reset hold time ta = 25 c 11.3 16.2 21.6 ms trst /reset pulse width ta = 25 c 2000 ? ? ns twdt watchdog timer duration ta = 25 c 11.3 16.2 21.6 ms tset input pin setup time ? ? 0 ? ns thold input pin hold time ? 15 20 25 ns tdelay output pin delay time cload=20pf 45 50 55 ns tdrc erc delay time ta = 25 c 1 3 5 ns note: 1. * n = selected prescaler ratio 2. twdt1: the option word1 (wdtps) is used to define the oscillator set-up time. wdt timeout length is the same as set-up time (18ms). 3. twdt2: the option word1 (wdtps) is used to define the oscillator set-up time. wdt timeout length is the same as set-up time (4.5ms). 4. these parameters are hypothetical (not tested) and are provided for design reference only. 5. data under minimum, typical, & maximum (min, typ, & max) columns are based on hypothetical results at 25 c. these data are for design reference use only. 6. the watchdog timer duration is determined by code option word1 (wdtps). www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 88 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) 10 timing diagrams reset timing (clk="0") clk /reset nop instruction 1 executed tdrh tcc input timing (clks="0") clk tcc ttcc tins ac testing : input is driven at vdd-0.5v for logic "1",and gnd+0.5v for logic "0".timing measurements are made at 0.75vdd for logic "1",and 0.25vdd for logic "0". ac test input/output waveform vdd-0.5v gnd+0.5v 0.75vdd 0.25vdd test points 0.75vdd 0.25vdd www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 89 (this specification is subject to change without further notice) appendix a. package type otp mcu package type pin count package size EM78P341Np dip 14 300mil EM78P341Nm sop 14 150mil em78p342np dip 18 300mil em78p342nm sop 18 300mil em78p343np dip 20 300mil em78p343nm sop 20 300mil em78p343nkm ssop 20 209mil b packaging configuration b.1 14-lead plastic du al in line (pdip) { 300 mil www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 90 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) b.2 14-lead plastic small outline (sop) { 150 mil www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 91 (this specification is subject to change without further notice) b.3 18-lead plastic du al in line (pdip) { 300 mil www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 92 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) b.4 18-lead plastic small outline (sop) { 300 mil www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 93 (this specification is subject to change without further notice) b.5 20-lead plastic shri nk small outline (ssop) { 209 mil www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 94 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) b.6 20-lead plastic dual-in-line (pdip) { 300 mil www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom product specification (v1.0) 12.01.2006 ? 95 (this specification is subject to change without further notice) b.7 20-lead plastic small outline (sopp) { 300 mil www.datasheet.net/ datasheet pdf - http://www..co.kr/
EM78P341N/342n/343n 8-bit microprocessor with otp rom 96 ? product specification (v1.0) 12.01.2006 (this specification is subject to change without further notice) c quality assurance and reliability test category test conditions remarks solderability solder temperature=245 5 c, for 5 seconds up to the stopper using a rosin-type flux ? step 1: tct, 65 c (15mins)~150 c (15mins), 10 cycles step 2: bake at 125 c, td (durance)=24 hrs step 3: soak at 30 c /60% d td (durance)=192 hrs pre-condition step 4: ir flow 3 cycles (pkg thickness 2.5mm or pkg volume 350mm 3 ----225 5 c) (pkg thickness 2.5mm or pkg volume 350mm 3 ----240 5 c ) for smd ic (such as sop, qfp, soj, etc) temperature cycle test -65 (15mins)~150 c (15mins), 200 cycles ? pressure cooker test ta =121 c, rh=100%, pressure=2 atm, td (durance) = 96 hrs ? high temperature / high humidity test ta=85 c , rh=85% d td (durance)=168 , 500 hrs ? high-temperature storage life ta=150 c, td (durance)=500, 1000 hrs ? high-temperature operating life ta=125 c, vcc=max. operating voltage, td (durance) =168, 500, 1000 hrs ? latch-up ta=25 c, vcc=max. operating voltage, 150ma/20v ? esd (hbm) ta=25 c, t ? 3kv t esd (mm) ta=25 c, t? 300v t ip_nd,op_nd,io_nd ip_ns,op_ns,io_ns ip_pd,op_pd,io_pd, ip_ps,op_ps,io_ps, vdd-vss(+),vdd_vss (-)mode c.1 address trap detect an address trap detect is one of the mcu embedded fail-safe functions that detects mcu malfunction caused by noise or the like. whenever the mcu attempts to fetch an instruction from a certain section of rom, an internal recovery circuit is auto started. if a noise caused address error is detected, the mcu will repeat execution of the program until the noise is eliminated. the mcu will then continue to execute the next program. www.datasheet.net/ datasheet pdf - http://www..co.kr/

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